6 of 6 UVM Jobs in the Thames Valley

design and verification of FPGA test benches and contribute to robust control systems for quantum hardware. You will own verification environments (SystemVerilog/UVM), drive constrained‐random testing and coverage, and help shape automated regression and CI pipelines. Hybrid work and competitive compensation are offered. #J-18808-Ljbffr ...

improved. What They're Looking For Experience managing or leading digital verification engineers Strong background in the verification of complex ICs Strong SystemVerilog and UVM experience, with knowledge of assertions and coverage-driven verification Experience developing verification strategies and using metrics such as code and functional coverage Ability to support ...

opportunities both for engineers looking to broaden their skills across the full lifecycle and for those who want to specialise in areas such as UVM-based verification. As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance … Master's degree in Electronic Engineering (or related field)Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metricsSystemVerilog UVM testbenchesFormal proof verificationUnderstanding of C test cases and C codeScripting languages (e.g. Python, Perl, TCL)Desirable skillsExperience with formal verification tools (JasperGold, VC Formal)Familiarity ...

edge verification methodologiesContribute to and Influence the decisions on methodologies/strategies to be adopted for design verification. Develop testbench architectures and develop using UVM or Formal based verification approaches. Define verification-plans, functional coverage, tests and verification methodology for block/chip-level verification. Work with the design team …/Processor subsystems/Formal verificationExpert in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration. Excellent debugging and analytical skills. Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.10-15 years ...

architect, and develop critical simulation infrastructure, contributing directly to the success of the FPGA team. Key responsibilities include Architect, develop, and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs. Define and execute comprehensive verification plans, including constrained‐random testing, functional coverage, and code coverage analysis. Collaborate with … strategies, and work collaboratively across design teams to ensure high‐quality outcomes. You'd be a great fit with Strong proficiency in SystemVerilog and UVM for architecting advanced verification environments. Experience using Python for test automation and scripting. Demonstrated ability to lead requirements gathering and define verification plans for complex ...

activities: demos, technical evaluations, benchmarks, methodology guidance Improve customer verification flows and testbench architectures Debug RTL/gate‐level simulation issues and SystemVerilog/UVM environments Analyse functional and code coverage Develop and debug SystemVerilog assertions Collaborate with Sales to grow adoption and identify new opportunities Act as the technical … voice of the customer to R&D What You’ll Need: Typically requires 8–13 yearsof relevant experience Strong knowledge ofVerilog/SystemVerilog, UVM, coverage, and assertions Experience in customer interaction, pre‐sales, or technical support is a plus Strong problem‐solving and communication skills Bachelor’s degree inComputer Engineering ...