5 of 5 UVM Jobs in the Thames Valley

in a related subject, with 5+ years of practical experience. Skills & Experience: Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and More ❯

the verification team. What You'll Need: In-depth understanding of verification flows, test plans, and strategies. Expertise in constrained-random SystemVerilog testbenches using UVM or VMM. Experience in creating and examining functional coverage and writing SystemVerilog assertions. Skills in debugging RTL and gate-level simulation failures and firmware. Familiarity More ❯

chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL or More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

UCIe, NVMe, Ethernet, USB, DDRx, HBM, AMBA. Knowledge of controllers for one or more high-speed interface protocols Expertise in coding with SystemVerilog, and UVM is mandatory Experience with integrating commercial VIP in SV/UVM bench required. Experience with Linux and Windows environments including scripting languages. Individual leadership and More ❯