26 to 42 of 42 Electronic Design Automation Jobs in the UK

System-on-Chips (SoC’s) to help shape our future products. The role shall be based in Basildon with a primary focus on the design and development of embedded VHDL firmware for complex airborne electro-optics subsystems. You will be part of the Leonardo Airborne Communications product development group … mitigating technical risk for Firmware design activities. Ability to communicate effectively across different disciplines both verbally and in written form. Familiarity with Siemens EDA FPGA development tools including HDL Designer and ModelSim/Questa is an advantage. It would be nice if you had Awareness of Safety, Security ...

Principal Design Team Leader Department: Hardware Employment Type: Permanent Location: Southampton, UK Description As the Principal Design Team Leader at AccelerComm, you will be working on 5G base stations on board satellites. This revolutionary technology is at the leading edge of non-terrestrial communications, and will underpin … timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis Expert user of EDA tools for simulation and synthesis Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability. ...

best run DevOps teams in the world choose Perforce. About the Role The Perforce IP Lifecycle Management (IPLM) suite - used by semiconductor and hardware design teams to manage their intellectual property (IP), releases, and dependencies at scale - includes a Python command-line client (pi), the IPLM API server … Have Prior experience building or maintaining a Python CLI used by other engineers as part of their daily workflow. Exposure to IP lifecycle management, EDA tooling, or the semiconductor/hardware design domain. Experience with basic development on Microsoft Windows; building and packaging Windows applications. Hands ...

best run DevOps teams in the world choose Perforce. About the Role The Perforce IP Lifecycle Management (IPLM) suite - used by semiconductor and hardware design teams to manage their intellectual property (IP), releases, and dependencies at scale - includes a Python command-line client (pi), the IPLM API server … Have: Prior experience building or maintaining a Python CLI used by other engineers as part of their daily workflow Exposure to IP lifecycle management, EDA tooling, or the semiconductor/hardware design domain Experience with basic development on Microsoft Windows; building and packaging Windows applications. Hands ...

Fractile is seeking a Senior/Principal Physical Design Engineer in Greater London. This role involves leading the physical implementation of advanced ASIC/SoC designs and collaboration with various teams to optimise performance, power, and area. The ideal candidate will … possess a Bachelor's, Master's or PhD in Electrical Engineering or a related field, along with 7+ years of relevant experience. Proficiency in EDA tools such as Cadence Innovus and a strong understanding of low-power design techniques are essential. Join us to pioneer in AI innovation. #J ...

About the Role The Perforce IP Lifecycle Management (IPLM) suite - used by semiconductor and hardware design teams to manage their intellectual property (IP), releases, and dependencies at scale - includes a Python command-line client (pi), the IPLM API server, the PiCache caching layer, and a Web based interface. … Have Prior experience building or maintaining a Python CLI used by other engineers as part of their daily workflow. Exposure to IP lifecycle management, EDA tooling, or the semiconductor/hardware design domain. Experience with basic development on Microsoft Windows; building and packaging Windows applications. Hands ...

neural accelerators is accelerating rapidly — and this company is at the forefront of that evolution. They are now looking for an experienced ASIC Design Engineer to join their Fabric IP team, bringing deep expertise in microarchitecture and RTL design to help shape the future of their technology portfolio. … Electrical Engineering, Computer Engineering, or Computer Science 8+ years of hands‐on experience in microarchitecture and RTL development Solid understanding of industry‐standard EDA tools and design methodologies Deep knowledge of on‐chip interconnects and NoCs Experience with cache coherency, memory subsystems, interconnects, or NoC IP is highly desirable ...

processors—including CPUs, GPUs, and neural accelerators and this is where you come in! You will be joining a Fabric IP company as a Design Verification Engineer, contributing your strong background in developing testbenches and writing test sequences for complex IPs. In this role, you will play a pivotal … years and current hands‐on experience in block‐level/IP‐level/SoC‐level verification Proficiency in Verilog, SystemVerilog Familiarity with industry‐standard EDA tools for simulation and debug Deep experience with UVM‐based testbenches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such ...

memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt. We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep … Your job is to develop the algorithms that exploit this natively: understand what transformer and diffusion workloads are well-suited to stochastic analog execution, design numerical methods that map onto the hardware's physical dynamics, and validate them against real silicon or high-fidelity simulation. This ...

will have proven experience in delivering industry‐leading verification quality and productivity under tight schedules. In this role the candidate will collaborate with architecture, design and central formal verification teams to define our formal verification roadmap, strategy, methodology, infrastructure and expand formal verification adoption through project execution. The candidate … engines and use cases Proven expertise in system Verilog assertion and abstract model development Expert user of formal verification tools from both academia and EDA vendors (JasperGold, VC formal, Murphi, theorem prover) Proven track record of delivering high quality verification under tight schedule for modern, large‐scale processor design ...

class engineering team based in Edinburgh, developing leading-edge IP for a wide range of high-tech markets. They are looking for a Senior Design Verification Engineer. As part of the Engineering group, you will play a key role in defining and driving the adoption of advanced verification tools … Power Verification Qualifications & required Skills Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline 4+ years’ experience in the microelectronics/EDA industry Proficiency in SystemVerilog and assertions Hands‐on experience with metric‐driven verification Strong knowledge of constrained‐random verification techniques (e.g. UVM) Experience with formal ...

Client: Our client a leading Multinational Semiconductor Company requires a Senior Principal Digital Front- End Design Engineer for role based in Edinburgh, Scotland. You will be required to be onsite 4 days per week. Role You will be apart of an experienced Front-End Engineering Team, working with Global … Industry Conferences such as IEEE, DAC, CDNLive Job Qualifications Degree inElectrical/ElectronicEngineering, Microelectronics, or a related discipline 12+ years’ experience in microelectronics/EDA industry Experience of Verilog RTL Design essential Experience of Metric Driven Verification (MDV) essential Experience of Front-end design tools covering LINT, Synthesis ...

Role Implement block-level and chip-level physical layouts for spin qubits in SiMOS quantum dots from concept through integration and tapeout using standard EDA tools. Drive layout work to completion using industry best practices to ensure manufacturability and scalability. Deliver layouts that meet agreed physical verification and sign … domains. Experience - Desirable Experience with quantum devices, CMOS process integration, and/or 3D integration. Experience developing PDKs, rule decks, or working closely with EDA teams. Scripting or automation experience (SKILL, Python, or similar). Experience managing a small team of layout engineers. Benefits Be part of a creative ...

AccelerComm Ltd in Southampton, UK, is seeking a Senior Design Engineer to join the Hardware department. You will develop RTL designs for ASIC/FPGA, contributing to space-qualified, high-throughput baseband processing … next-gen communications. You will collaborate with Algorithm and System Architecture teams, implement testbenches, and optimize timing and resources while using industry-standard EDA tools to meet project milestones. On-site role with exciting frontier tech. #J-18808-Ljbffr ...

Resources is seeking a skilled Senior Physical Design Engineer to drive the development of advanced multi-core in-memory compute SoCs in the United Kingdom. You will be integral to high-performance ASIC projects, leading full-chip physical design … tasks and collaborating with cross-functional teams. Ideal candidates should have extensive knowledge of ASIC physical design, along with hands-on experience with EDA tools and strong scripting abilities. This role offers the opportunity to work in a fast-paced, innovative environment. #J-18808-Ljbffr ...

quality and bring down costs, then this is the role for you. You’ll work closely with colleagues across modelling, system architecture, and RTL design to ensure our RTL releases meet the highest standards of functional quality. That includes contributing to discussions around specification, architecture, and the workflows that … Assertions (SVA) Software fluency in multiple languages Open source tools for silicon development Cocotb (used for all our testbench collateral), Verilator, Icarus Verilog Commercial EDA tools Formal verification Bazel is our chosen tool, familiarity is not expected Contributing to architecture discussions How we work Ownership and execution: you will have ...

Cadence in the United Kingdom seeks a Principal Product Engineer – Custom Layout & Virtuoso Applications to bridge Cadence’s design tools with strategic customers in custom analog … FinFet design. The role drives technical depth and cross‐functional collaboration, translating real customer challenges into product improvements for the Cadence ecosystem and broader EDA community. You will engage with customers, guide adoption, contribute to product roadmap, and mentor junior engineers. #J-18808-Ljbffr ...