51 to 75 of 78 Perl Jobs in the UK

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Peterborough, Cambridgeshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Dartford, Kent, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
South London, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Northampton, Northamptonshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Lincoln, Lincolnshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Norwich, Norfolk, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Bedford, Bedfordshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Colchester, Essex, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Oxford, Oxfordshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Bournemouth, Dorset, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Cheltenham, Gloucestershire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Reading, Berkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Ipswich, Suffolk, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
East Anglia, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Wakefield, West Yorkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Hemel Hempstead, Hertfordshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Stockport, Greater Manchester, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Newport, Isle of Wight, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Hull, East Yorkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Newcastle upon Tyne, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Crawley, West Sussex, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
York, North Yorkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Brighton, East Sussex, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
North East, Glasgow, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Design Verification Engineer

Hiring Organisation
IC Resources
Location
Edinburgh, Scotland, United Kingdom
like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Edinburgh. This is a hybrid remote position and will follow a 2+ ...