Design Verification Engineer
- Location
- City of Edinburgh, Scotland, United Kingdom
Functional and code coverage analysis Strong SystemVerilog, including SVA (SystemVerilog Assertions) Testbench development using verification frameworks (e.g. UVM) Strong debugging skills Scripting experience with TCL or Perl Power-aware verification using CPF/UPF Formal verification and verification qualification techniques (nice to have) This is a truly superb opportunity ...