76 to 100 of 129 PCIe Jobs in the UK excluding London

mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications and protocols for high-speed interfaces - PCIe, USB, Ethernet etc Algorithm development 3 Locations available: UK Germany Switzerland ...

mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications and protocols for high-speed interfaces - PCIe, USB, Ethernet etc Algorithm development 3 Locations available: UK Germany Switzerland ...

mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications and protocols for high-speed interfaces - PCIe, USB, Ethernet etc Algorithm development 3 Locations available: UK Germany Switzerland ...

mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications and protocols for high-speed interfaces - PCIe, USB, Ethernet etc Algorithm development 3 Locations available: UK Germany Switzerland ...

mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications and protocols for high-speed interfaces - PCIe, USB, Ethernet etc Algorithm development 3 Locations available: UK Germany Switzerland ...

mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications and protocols for high-speed interfaces - PCIe, USB, Ethernet etc Algorithm development 3 Locations available: UK Germany Switzerland ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as LPDDR, Ethernet, PCIe, HBM, CPUs, Low-Speed IOs (UART, I2C, I3C, SPI), and Coherent Mesh. Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation ...

i.mX. Interfacing with a range of Analogue, Digital and Electromechanical components and sensors. Basic Graphic User Interfaces Communication Interfaces (e.g. USB3.2, MIPI, PCIe, I2C, SPI). Camera, Motor and Temperature Control. Lighting control (e.g. Lasers, LEDs, flash lamps). Basic safety critical circuits. If interested, and you match the criteria ...

solid understanding of SoC architectures, memory interfaces, and platform design in embedded compute or related fields. Proven experience with high-speed interface standards (e.g., PCIe Gen5/6, LPDDR5/6) and associated peripherals. Hands-on experience with embedded system board design, including complex LSI devices such as FPGAs, embedded ...

experience with SoC architectures, memory interfaces, and platforms involving embedded compute or AI. High-Speed Interconnects: Hands-on experience with cutting-edge standards, specifically PCIe Gen5/6 and LPDDR5/6 . Complex Board Design: Proven competence in designing boards with high-complexity LSI devices (FPGAs), embedded firmware ...

experience with SoC architectures, memory interfaces, and platforms involving embedded compute or AI. High-Speed Interconnects: Hands-on experience with cutting-edge standards, specifically PCIe Gen5/6 and LPDDR5/6 . Complex Board Design: Proven competence in designing boards with high-complexity LSI devices (FPGAs), embedded firmware ...

Nice to have Understanding of the channel ecosystem (distributors, sub distributors, refurb, brokers). Familiarity with server architecture, product SKUs, binning, TDP, memory channels, PCIe lanes, etc. Awareness of AI and ML or HPC workloads and the networking demands behind them (40/100/200/400GbE, optics). ...

agility. Role Overview Functional Validation of a new SOC designed with high end ARM processors Functional Bring-up of SOC interfaces like LPDDR, Ethernet, PCIe, HBM, CPU's, Low speed Ios (UART, I2C, I3C, SPI), Coherent Mesh etc. Develop bare metal C tests and debug using FPGA HAPS/Zebu … with other stakeholders: Architects, RTL verification, Electrical testing & characterization, Production firmware Essential skills: Strong in Embedded C, any of the high speed protocol experience (PCIe Gen6, die to die links, LPDDR5, HBM3), ARM high end CPUs, ARM cache coherent interconnect protocol, and validation experience on pre/post Si platforms. ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as: LPDDR Ethernet PCIe HBM CPUs Low-Speed IOs (UART, I2C, I3C, SPI) Coherent Mesh Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation platforms … Verification teams Electrical Testing & Characterization teams Production Firmware teams Essential Skills Strong proficiency in Embedded C . Experience with high-speed protocols such as: PCIe Gen6 Die-to-die links LPDDR5 HBM3 Hands-on expertise with ARM high-end CPUs and ARM cache-coherent interconnect protocols . Proven validation experience ...

Description: Functional Validation of a new SOC designed with high end ARM processors Functional Bring-up of SOC interfaces like – LPDDR, Ethernet, PCIe, HBM, CPU’s, Low speed Ios (UART, I2C, I3C, SPI), Coherent Mesh etc. Develop bare metal C tests and debug using FPGA HAPS/Zebu emulation platforms … with other stakeholders: Architects, RTL verification, Electrical testing & characterization, Production firmware Essential skills: Strong in Embedded C, any of the high speed protocol experience (PCIe Gen6, die to die links, LPDDR5, HBM3), ARM high end CPUs, ARM cache coherent interconnect protocol, and validation experience on pre/post Si platforms. ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as LPDDR, Ethernet, PCIe, HBM, CPUs, Low-Speed IOs (UART, I2C, I3C, SPI), and Coherent Mesh. Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation … Architects, RTL Verification, Electrical Testing & Characterization, and Production Firmware teams. Essential Skills Strong proficiency in Embedded C. Experience with high-speed protocols such as PCIe Gen6, die-to-die links, LPDDR5, and HBM3. Hands-on expertise with ARM high-end CPUs and ARM cache-coherent interconnect protocols. Proven validation experience ...

functional validation of next-generation SoC designs based on high-performance ARM processors. Lead functional bring-up of critical SoC interfaces, including LPDDR, Ethernet, PCIe, HBM, CPUs, low-speed peripherals (UART, I2C, I3C, SPI), and cache-coherent mesh interconnects. Create and debug bare-metal C test software using FPGA HAPS … Electrical Test & Characterization, and Production Firmware groups. Essential Skills Advanced proficiency in Embedded C development. Strong experience with high-speed interfaces and protocols, including PCIe Gen6, die-to-die links, LPDDR5, and HBM3. In-depth hands-on experience with high-end ARM CPUs and ARM cache-coherent interconnect technologies. Demonstrated ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...

based verification environments Perform constrained-random verification and coverage closure Integrate and customize VIP for high-speed interfaces Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Automate verification flows using Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado …/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity with AMD Vivado/Vitis tools ...