metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯
based firmware development lifecycle to deliver customer requirements by: Developing high-level firmware requirements using DOORS Creating architectural designs Defining low level requirements and detailed designs Writing VHDL and Verilog HDL code using Sigasi Studio Simulating HDL designs at unit, integration and system level using Mentor Graphics QuestaSIM Undertaking synthesis, place and route and static timing analysis using Synopsis Synplify More ❯
intricately involved in creating next generation FPGA solutions to support ultra-low latency trading systems across the firm. The ideal candidate should have a strong background in in System Verilog or VHDL, as well as software engineering. The candidate must have a keen interest in using software engineering methodologies to improve the efficiency of the hardware development workflow, as well … Engineering, Computer Science or similar 5+ years professional experience as an FPGA Developer either in or outside of the finance/trading industry Experienced and well-versed in System Verilog or VHDL (Python, C, Tcl, and bash a plus) Experience in one or more of the following areas: Hardware Architecture, RTL Coding, Simulation, Systems Integration, Hardware Validation and Testing, FPGA More ❯
Southampton, England, United Kingdom Hybrid / WFH Options
Octagon Group
The job: Leading and mentoring a team of FPGA engineers Owning the technical direction for FPGA development across several product lines Designing and developing FPGA solutions using VHDL or Verilog Overseeing verification, validation, and integration of designs Working on high-performance designs, often involving video or RF signal processing The ideal candidate: A degree in Electrical Engineering, Computer Science, or … something similar At least 10 years of hands-on FPGA design experience Comfortable leading others and making technical decisions Solid experience with VHDL or Verilog and common FPGA toolsets A good grasp of high-speed digital design You’ll need to be eligible for UK Security Clearance The offer: Salary up to £75,000 (depending on experience) Hybrid working and More ❯
