Principal ASIC Design Engineer
- Hiring Organisation
- Intellectual Capital Resources
- Location
- Cambridge, Cambridgeshire, United Kingdom
- Salary
- £ 70 K
design (SystemVerilog), verification methodologies (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints. Familiarity with scripting languages such as Bash, Python, or Tcl. Please note that this role is based in Cambridge and requires full-time onsite attendance. This opportunity offers a fantastic compensation ...