251 to 275 of 285 Field-Programmable-Gate-Array Jobs

Do you want to work on some of the most advanced technology in the world? Our client operates one of the most powerful private HPC clusters globally, with 10s of thousands of GPUs (including 1000s of A100s), 100s of petabytes More ❯

Do you want to work on some of the most advanced technology in the world? Our client operates one of the most powerful private HPC clusters globally, with 10s of thousands of GPUs (including 1000s of A100s), 100s of petabytes More ❯

Do you want to work on some of the most advanced technology in the world? Our client operates one of the most powerful private HPC clusters globally, with 10s of thousands of GPUs (including 1000s of A100s), 100s of petabytes More ❯

Do you want to work on some of the most advanced technology in the world? Our client operates one of the most powerful private HPC clusters globally, with 10s of thousands of GPUs (including 1000s of A100s), 100s of petabytes More ❯

FPGA Engineer Farnborough - £65,000 - £75,000 I am working with a specialist technology business in Farnborough that design and develop secure hardware solutions for government and defence applications. Their work focuses on protecting sensitive information through innovative engineering, ensuring critical data remains safe, and reliable click apply for full job details More ❯

Provide managerial leadership to build knowledge and support the team development. Work closely with the exec team to translate product requirements into hardware team deliverables. Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches. Lead engineering methodology, processes and design techniques. Nurture professional growth of team members through regular mentoring, coaching … and feedback Skills, Knowledge & Expertise: Track record of building and leading high performing collaborative teams. Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products. A strong skillset in delivery of digital designs for ASIC and FPGA. Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques More ❯

Provide managerial leadership to build knowledge and support the team development. Work closely with the exec team to translate product requirements into hardware team deliverables. Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches. Lead engineering methodology, processes and design techniques. Nurture professional growth of team members through regular mentoring, coaching … and feedback Skills, Knowledge & Expertise: Track record of building and leading high performing collaborative teams. Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products. A strong skillset in delivery of digital designs for ASIC and FPGA. Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques More ❯

About Us: Were a small team of ECE students and recent grads whove interned at hardware companies and just ran the gauntlet for ASIC/DV/FPGA roles. We built (link removed) to fix a real gap: interview questions for hardware engineers are scattered across Discords and DMs. Our platform organizes vetted, real interview questions by company, role, and … and Supabase RPCs to React/Next.js UI and Vercel deployments. Youll ship fast, talk to users, and help us scale a community-driven question bank covering DV, RTL, FPGA, Embedded/Firmware, Analog, PD, and more. We have multiple features in our mind we are willing to share in the interview round. This remote position is for 8 months … computer science. Nice To Haves: (we would love to see these) Knowledge about database security (because we don't know this) Interest in Hardware/ASIC/DV/FPGA/Embedded, or curiosity to learn the domain fast. More ❯

data, and infrastructure components Performance engineering at every layer: CPU, cache, memory, and network Profile, benchmark, and fine-tune system behaviour under real-world conditions Collaborate with hardware and FPGA engineers on end-to-end architecture design Kernel-level optimization and low-level systems tuning Required: 5+ years developing performance-critical C++ applications (modern C++ standards) Strong systems programming and … tools Genuine curiosity about hardware behaviour, networking, and system optimization Why Join: Work on systems where nanosecond optimizations have measurable impact Collaborate with world-class engineers across disciplines (software, FPGA, infrastructure) Technology-first culture that values innovation and technical excellence Solve challenging problems at the cutting edge of performance engineering More ❯

data, and infrastructure components Performance engineering at every layer: CPU, cache, memory, and network Profile, benchmark, and fine-tune system behaviour under real-world conditions Collaborate with hardware and FPGA engineers on end-to-end architecture design Kernel-level optimization and low-level systems tuning Required: 5+ years developing performance-critical C++ applications (modern C++ standards) Strong systems programming and … tools Genuine curiosity about hardware behaviour, networking, and system optimization Why Join: Work on systems where nanosecond optimizations have measurable impact Collaborate with world-class engineers across disciplines (software, FPGA, infrastructure) Technology-first culture that values innovation and technical excellence Solve challenging problems at the cutting edge of performance engineering More ❯

data, and infrastructure components Performance engineering at every layer: CPU, cache, memory, and network Profile, benchmark, and fine-tune system behaviour under real-world conditions Collaborate with hardware and FPGA engineers on end-to-end architecture design Kernel-level optimization and low-level systems tuning Required: 5+ years developing performance-critical C++ applications (modern C++ standards) Strong systems programming and … tools Genuine curiosity about hardware behaviour, networking, and system optimization Why Join: Work on systems where nanosecond optimizations have measurable impact Collaborate with world-class engineers across disciplines (software, FPGA, infrastructure) Technology-first culture that values innovation and technical excellence Solve challenging problems at the cutting edge of performance engineering More ❯

data, and infrastructure components Performance engineering at every layer: CPU, cache, memory, and network Profile, benchmark, and fine-tune system behaviour under real-world conditions Collaborate with hardware and FPGA engineers on end-to-end architecture design Kernel-level optimization and low-level systems tuning Required: 5+ years developing performance-critical C++ applications (modern C++ standards) Strong systems programming and … tools Genuine curiosity about hardware behaviour, networking, and system optimization Why Join: Work on systems where nanosecond optimizations have measurable impact Collaborate with world-class engineers across disciplines (software, FPGA, infrastructure) Technology-first culture that values innovation and technical excellence Solve challenging problems at the cutting edge of performance engineering More ❯

data, and infrastructure components Performance engineering at every layer: CPU, cache, memory, and network Profile, benchmark, and fine-tune system behaviour under real-world conditions Collaborate with hardware and FPGA engineers on end-to-end architecture design Kernel-level optimization and low-level systems tuning Required: 5+ years developing performance-critical C++ applications (modern C++ standards) Strong systems programming and … tools Genuine curiosity about hardware behaviour, networking, and system optimization Why Join: Work on systems where nanosecond optimizations have measurable impact Collaborate with world-class engineers across disciplines (software, FPGA, infrastructure) Technology-first culture that values innovation and technical excellence Solve challenging problems at the cutting edge of performance engineering More ❯

planet, where every microsecond is contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C+/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L - measured, profiled, and deployed in live markets where performance is the edge. They're now seeking an elite C++ … Engineer branch-prediction-aware order handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C+/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using perf , VTune , bcc , and FlameGraphs More ❯

planet, where every microsecond is contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C++20/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L — measured, profiled, and deployed in live markets where performance is the edge. They’re now seeking an elite C++ … Engineer branch-prediction-aware order handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C++20/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using perf , VTune , bcc , and FlameGraphs More ❯

planet, where every microsecond is contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C++20/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L — measured, profiled, and deployed in live markets where performance is the edge. They’re now seeking an elite C++ … Engineer branch-prediction-aware order handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C++20/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using perf , VTune , bcc , and FlameGraphs More ❯

planet, where every microsecond is contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C++20/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L — measured, profiled, and deployed in live markets where performance is the edge. They’re now seeking an elite C++ … Engineer branch-prediction-aware order handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C++20/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using perf , VTune , bcc , and FlameGraphs More ❯

planet, where every microsecond is contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C++20/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L — measured, profiled, and deployed in live markets where performance is the edge. They’re now seeking an elite C++ … Engineer branch-prediction-aware order handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C++20/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using perf , VTune , bcc , and FlameGraphs More ❯

planet, where every microsecond is contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C++20/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L — measured, profiled, and deployed in live markets where performance is the edge. They’re now seeking an elite C++ … Engineer branch-prediction-aware order handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C++20/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using perf , VTune , bcc , and FlameGraphs More ❯

A-600 inspections. Schematic capture and PCB layout using tools such as OrCAD, PADS (or equivalent) with focus on stack-up, power integrity and signal integrity. Collaborate closely with FPGA/ASIC teams, firmware/embedded engineers and mechanical designers to optimise overall system performance and manufacturability. Author and execute hardware bring-up, validation and test plans; drive prototype evaluation … and SerDes interface design. Demonstrated ability to work in a cross-functional international team (hardware, firmware, mechanical) and drive projects end-to-end. Nice-to-have experience: Experience with FPGA-based board design or embedded systems. Familiarity with industrial standards such as EN55032/35, EN61000-6-4, EN50155, IEC or MIL-STD-810 for ruggedised applications. Previous involvement in More ❯

Our client BAE Systems are seeking a Digital Hardware Engineering Lead for a contract position to support a Radar programme. This is based in Cowes, on the Isle of Wight and will require onsite working, 3-4 days per week. More ❯

About Us Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up and spec to product. With 3200+ employees worldwide, Tessolve delivers a one-stop solution with advanced More ❯

🔎 Hardware Engineer | Cutting-Edge Electronics | Oxford (Hybrid) We’re supporting an emerging deep-tech company developing next-generation hybrid photonic systems that push the boundaries of computing. As a Hardware Engineer, you’ll play a key role in designing, testing More ❯

About Us Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up and spec to product. With 3200+ employees worldwide, Tessolve delivers a one-stop solution with advanced More ❯

🔎 Hardware Engineer | Cutting-Edge Electronics | Oxford (Hybrid) We’re supporting an emerging deep-tech company developing next-generation hybrid photonic systems that push the boundaries of computing. As a Hardware Engineer, you’ll play a key role in designing, testing More ❯