debug on RTL and Gate Level Netlist Hands-on knowledge in state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting more »
debug on RTL and Gate Level Netlist Hands-on knowledge in state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting more »
gate level verification, silicon debug, memory and scan diagnostics. Experience coding Verilog RTL, TCL and/or Perl Experience with Cadence, and/or Synopsys DFT and simulation tools "Nice To Have" Skills and Experience : Familiarity with SoC style architectures including multi-clock domain and low power design practices. Previous more »
Background in design, implementation and timing convergence is a plus Experience in leading datacenter SOCs is a plus. Experience with Cadence, and/or Synopsys DFT and simulation tools Salary Range: From:$283,305 To: $383,295 We value people as individuals and our dedication is to reward people competitively more »
development, electronic design automation (EDA) area, algorithm development or a related technical area Proficiency with SPICE-simulators (e.g., SIMetrix, Orcad PSpice, LTspice, Cadence Spectre, Synopsys HSPICE, Siemens EDA AFS, etc.) Good programming skills with focus on C++/C A deep understanding of electronic devices and their applications Understanding in more »
techniques Self-motivation with excellent interpersonal and problem-solving skills Some hands-on experience with SPICE-simulators (e.g.,SIMetrix, Orcad PSpice, LTspice, Cadence Spectre, Synopsys HSPICE,Siemens EDA AFS, etc.) or simulation frameworks (e.g., MATLAB/Simulink,COSIDE, etc.) Excellent spoken and written communication skills in English, German language skills more »
Cambridge, Cambridgeshire, East Anglia, United Kingdom Hybrid / WFH Options
Langham Recruitment Limited
basis for 6 months. Responsibilities & Experience: Excellent ATPG/MBIST skills are required. Experience building a new flow from scratch. Must be familiar with Synopsys/Cadence/Mentor industry standard toolsets. Previous experience of EDA tool specification/procurement is nice to have Strong ATE bring up and production more »
Employment Type: Contract, Work From Home
Rate: £60 - £80 per hour, Benefits Outside IR35 Hybrid
Cambridge, Cambridgeshire, East Anglia, United Kingdom
Bluegate Consulting Ltd
synthesis, STA, test insertion, MBIST, formality, GDS layout etc Experience in EDA tools for custom IC development like Siemens Questa for simulation and verification, Synopsys DesignCompiler for synthesis and STA, Spyglass for linting, etc. Good knowledge of UVM, SVA, VIP, and UPF for digital IC design verification If you are more »
Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, designing and conducting experiments/tool evaluations. Experience with Siemens, Cadence and/or Synopsys DFT tools "Nice To Have" Skills and Experience : Ability to build and deploy generic DFT flows Familiarity with IEEE standards such as 1500, 1149.1 more »
