51 to 56 of 56 Xilinx Jobs

requested information, as laid out in the job overview below. Looking for an ambitious, proactive self-starter who identifies problems and takes ownership Xilinx RFSoC and/or Software Defined Radio experience required 5+ yrs experience Strong focus on VHDL development on AMD Xilinx platforms (Vivado) DSP expertise required Experience ...

business delivering high-performance FPGA systems into mission-critical environments. As an FPGA Engineer, based in Bristol you will specialise in; Proven experience with Xilinx RFSoC and/or Software Defined Radio (SDR) systems Strong mathematical DSP fundamentals VHDL design targeting Xilinx/AMD xkybehq devices using Vivado APPLY ...

potential candidates, as well as how to apply Good luck. Looking for an ambitious, proactive self-starter who identifies problems and takes ownership Xilinx RFSoC and/or Software Defined Radio experience required 5+ yrs experience Strong focus on VHDL development on AMD Xilinx platforms (Vivado) DSP expertise required Experience ...

business delivering high-performance FPGA systems into mission-critical environments. As an FPGA Engineer, based in Bristol you will specialise in; Proven experience with Xilinx RFSoC and/or Software Defined Radio (SDR) systems Strong mathematical DSP fundamentals VHDL design targeting Xilinx/AMD xkybehq devices using Vivado APPLY ...

potential candidates, as well as how to apply Good luck. Looking for an ambitious, proactive self-starter who identifies problems and takes ownership Xilinx RFSoC and/or Software Defined Radio experience required 5+ yrs experience Strong focus on VHDL development on AMD Xilinx platforms (Vivado) DSP expertise required Experience ...

Socode are seeking a hands-on RTL FPGA engineer who will be building a real-time 12G-SDI video pipeline on Xilinx Zynq UltraScale+ for a 9-month contract in Cambridge, UK. You will: Implement uncompressed UHD 12G-SDI capture and transmit (SMPTE standards) Design full-frame alpha-blended compositing … rates Close timing in Vivado at UHD bandwidths Develop simulation testbenches and perform hardware validation Measure and optimise deterministic, sub-frame latency Required experience: Xilinx Vivado and Zynq PS/PL architecture 3G/6G/12G-SDI implementation in FPGA Frame/line buffer design and high-bandwidth ...