Senior Design Lead
- Location
- Cambridge, England, United Kingdom
regression failure analysis Functional and Code Coverage closure participate in verification closure Experience in Perl/Shell scripting EducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field Core Technical Skills Languages: Proficiency in Verilog, SystemVerilog … regression failure analysis Functional and Code Coverage closure participate in verification closure Experience in Perl/Shell scripting EducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field Core Technical Skills Languages: Proficiency in Verilog, SystemVerilog ...