51 to 75 of 81 Electronic Design Automation Jobs in England

Design Team Leader Department: Hardware Employment Type: Full Time Location: Bristol Description As the Principal Design Team Leader at AccelerComm, you will be working on 5G base stations on board satellites. This revolutionary technology is at the leading edge of non-terrestrial communications, and will underpin the next … timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis Expert user of EDA tools for simulation and synthesis Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability. ...

Senior FPGA/ASIC Design Engineers - 5G & Satellite Technology Spectrum IT Recruitment is working with a cutting-edge technology business in Southampton that is expanding its engineering team and looking for multiple Senior Design Engineers with strong FPGA/ASIC experience. This is an opportunity to work … synthesis and timing analysis Knowledge of high-throughput data or signal-processing designs Experience optimising timing and hardware resources Strong knowledge of industry-standard EDA simulation and synthesis tools Experience delivering complex, integrated digital designs Additional experience with 5G, communications/DSP algorithms, UVM, AMBA, SystemC/C++, PCIe, JESD ...

System-on-Chips (SoC’s) to help shape our future products.The role shall be based in Basildon with a primary focus on the design and development of embedded VHDL firmware for complex airborne electro-optics subsystems.You will be part of the Leonardo Sensors product development group within the Integrated … mitigating technical risk for Firmware design activities.* Ability to communicate effectively across different disciplines both verbally and in written form.* Familiarity with Siemens EDA FPGA development tools including HDL Designer and ModelSim/Questa is an advantage.**It would be nice if you had:*** Awareness of Safety, Security ...

Senior FPGA/ASIC Design Engineers - 5G & Satellite Technology Remember to check your CV before applying Also, ensure you read through all the requirements related to this role. Spectrum IT Recruitment is working with a cutting-edge technology business in Southampton that is expanding its engineering team and looking … synthesis and timing analysis Knowledge of high-throughput data or signal-processing designs Experience optimising timing and hardware resources Strong knowledge of industry-standard EDA simulation and synthesis tools Experience delivering complex, integrated digital designs Additional experience with 5G, communications/DSP algorithms, UVM, AMBA, SystemC/C++, PCIe, JESD ...

next-generation compute architectures, developing high-performance, power-efficient CPU technology on the most advanced process nodes, is looking for an experienced Physical Design Engineer to join its growing team. You will play a key role in the implementation of cutting-edge CPU IP within a world-class engineering …/SoC designs Experience across the full implementation flow including floorplanning, place and route, CTS and physical sign-off Familiarity with industry-standard EDA tools such as Innovus, ICC2, Fusion Compiler or equivalent Good understanding of timing closure, power optimisation and physical verification methodologies Strong scripting skills with TCL, Python ...

early production, with a focus on high-speed FPGA and SoC development for complex embedded applications. Key Responsibilities Capture and manage firmware requirements Design, develop, and analyse FPGA-based firmware (VHDL) Produce technical documentation and support design reviews Develop test, verification, and integration plans Collaborate with hardware … full firmware lifecycle within structured standards (e.g. DO-254 or similar) Debugging and integration at hardware/system level Desirable Familiarity with Siemens EDA tools (e.g. ModelSim, Questa, HDL Designer) Experience with safety-critical standards (e.g. IEC 61508) Exposure to electro-optic or imaging systems ...

early production, with a focus on high-speed FPGA and SoC development for complex embedded applications. Key Responsibilities Capture and manage firmware requirements Design, develop, and analyse FPGA-based firmware (VHDL) Produce technical documentation and support design reviews Develop test, verification, and integration plans Collaborate with hardware … full firmware lifecycle within structured standards (e.g. DO-254 or similar) Debugging and integration at hardware/system level Desirable Familiarity with Siemens EDA tools (e.g. ModelSim, Questa, HDL Designer) Experience with safety-critical standards (e.g. IEC 61508) Exposure to electro-optic or imaging systems #J-18808-Ljbffr ...

early production, with a focus on high-speed FPGA and SoC development for complex embedded applications. Key Responsibilities Capture and manage firmware requirements Design, develop, and analyse FPGA-based firmware (VHDL) Produce technical documentation and support design reviews Develop test, verification, and integration plans Collaborate with hardware … full firmware lifecycle within structured standards (e.g. DO-254 or similar) Debugging and integration at hardware/system level Desirable Familiarity with Siemens EDA tools (e.g. ModelSim, Questa, HDL Designer) Experience with safety-critical standards (e.g. IEC 61508) Exposure to electro-optic or imaging systems ...

understanding through to tape-out. Define system architecture, instruction set architecture (ISA) and dataflow models based on workload requirements. Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements. Build functional simulations and performance models to guide architectural decisions. Conduct timing, power … architectural trade-off analysis using Python, C++ or similar languages. Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools. Solid understanding of timing, power and area optimisation at the architectural level. Experience defining hardware/software interfaces and collaborating with firmware and compiler teams. ...

understanding through to tape-out. Define system architecture, instruction set architecture (ISA) and dataflow models based on workload requirements. Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements. Build functional simulations and performance models to guide architectural decisions. Conduct timing, power … architectural trade-off analysis using Python, C++ or similar languages. Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools. Solid understanding of timing, power and area optimisation at the architectural level. Experience defining hardware/software interfaces and collaborating with firmware and compiler teams. ...

System-on-Chips (SoC’s) to help shape our future products. The role shall be based in Basildon with a primary focus on the design and development of embedded VHDL firmware for complex airborne electro-optics subsystems. You will be part of the Leonardo Sensors product development group within … technical decisions and mitigating technical risk forFirmware designactivities. Ability to communicate effectively across different disciplines both verbally and in written form. Familiarity with Siemens EDA FPGA development tools including HDL Designer and ModelSim/Questa is an advantage. It would be nice if you had: Awareness of Safety, Security ...

Design Team Leader Department: Hardware Employment Type: Full Time Location: Cambridge Description As the Principal Design Team Leader at AccelerComm, you will be working on 5G base stations on board satellites. This revolutionary technology is at the leading edge of non-terrestrial communications, and will underpin the next … timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis Expert user of EDA tools for simulation and synthesis Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability. ...

Overview: We are looking for an EDA Optimisation Engineer to support the data-driven optimisation, analysis and maintenance of Arm’s engineering platforms. This role will work as part of a team effort to improve system utilisation/efficiency/cost-performance and touch on forecasting accuracy and infrastructure strategy. … finance teams to ensure data-driven decision making. Required Skills and Experience : Background in distributed HPC, cloud environments, data engineering & analytics. Knowledge of EDA workflows and semiconductor engineering environments. Proficiency in Python and data analysis/ML frameworks. Ability to turn sophisticated data into clear, actionable strategy. “Nice To Have ...

Synopsys, Inc. is seeking an experienced ASIC Digital Design Engineer to drive RTL design and verification for complex blocks and systems. You will collaborate with Analog, physical design, and applications engineering to ensure integration and performance meet demanding specifications. You will develop comprehensive test plans, optimize performance and power with advanced EDA methodologies, and mentor junior engineers while staying current with industry trends to deliver high-quality, reliable #J-18808-Ljbffr ...

Seoul. The Role As an Analog Hardware Engineer, you will build the core mixed-signal technology powering our unconventional computing architecture. You will design unique analog circuits, creating library cells as well as macros, to support a unique computational architecture. Working alongside silicon architecture, digital, and layout teams … full analog development cycle including research, exploratory design Develop or acquire analog IP for use in Normal Silicon Acquire or help direct analog EDA tool development Evaluation of memory designs, including SRAM, DRAM, and CIM architectures What Makes You a Great Fit Developed analog IP from spec to GDSII ...

AccelerComm is hiring a Hardware Design Engineer in Southampton to contribute to next-gen non-terrestrial communications and space-qualified devices. You will translate requirements into RTL architectures and implement FPGA/ASIC designs with … testbenches, collaborating with architecture, verification and physical implementation teams to deliver high-performance IP. The role involves working with Verilog/SystemVerilog/VHDL, EDA tools, and advanced interfaces; a strong emphasis on verification #J-18808-Ljbffr ...

Quantum Motion is seeking a Principal EDA Engineer to drive the EDA environment, support tape-out and interface with foundries for advanced CMOS ASICs. You will lead a multidisciplinary team and shape the flow from concept to volume production in a cutting-edge quantum computing program. The role requires deep ...

Limited in Cambridge is seeking an EDA Optimisation Engineer to drive data-driven optimisation, analysis and maintenance of Arm’s engineering platforms. You will help improve system utilisation, efficiency and cost-performance across HPC compute, cloud, Emulation and FPGA environments. In a metrics-first environment, you will develop dashboards, pipelines ...

high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements Modern semiconductor process technologies including 28nm, 14/16nm, 7nm EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop ...

scan, compression, MBIST, LBIST, boundary scan) Set DFT strategy, methodology, flow and signoff criteria Drive integration of DFT tools and flows into the overall EDA environment Define hierarchical DFT approach for multi-core designs and large memory systems Define scan architecture, compression strategy, and ATPG approach Define memory test … repair strategy for large embedded RAM Establish power-aware and at-speed test strategies Work closely with RTL and physical design to ensure clean DFT integration and timing closure Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test ...

familiarity with ThinX, HDX, PCoIP, or related protocols. Experience managing distributed Linux environments across on-premises, HPC, hybrid-cloud, or multi-cloud infrastructure. Semiconductor, EDA, or engineering compute experience is helpful. Proficiency in automation using tools such as Terraform, Ansible, Python, Bash, GitLab CI/CD, and REST APIs … Grafana, ELK/OpenSearch, Splunk, CloudWatch, or similar tools. Understanding of SRE and modern operations practices, including incident resolution, capacity management, AIOps, policy-based automation, self-healing services, and operational toil reduction. Contribute to the future evolution of engineering access services through self-service workflows, policy-aware automation ...

Nordic Semiconductor is seeking a Front-End Design Engineer to contribute to the next generation of Wi‐Fi SoCs. You will work on digital IC design from architecture to tape-out, collaborating with architecture, verification, software … implementation teams to deliver high-quality silicon solutions. The role requires strong RTL/verification experience, RTL languages (SystemVerilog/Verilog/VHDL), EDA tools, and proficiency in scripting. #J-18808-Ljbffr ...

computing through automated, bespoke design. One-size-fits-all GPU/NPU accelerator architectures woefully underutilise available compute; at Heronic we turn the design paradigm on its head, creating specialised architectures that reach near 100% occupancy. With and backing from VCs and Angels including the co-founder … software teams.**Experience:*** Prior experience developing verification plans.* Experience with AXI protocols.* Familiar with open-source verification tools (Cocotb, Verilator) as well as commercial EDA tools.* Experience with scripting languages (Python, Tcl) for automation.* Familiar with CI/CD infrastructure.* Familiarity with transaction-level modelling (UVM).* Comfortable with version ...

volume, resolution times, top causes, and work removed by automation. What this role does not cover: designing or building new platforms, owning the EDA platform build programme, end-user IT support (laptops, phones, Microsoft 365, identity provisioning - these stay with the IT support team), or security incident response. Skills & Experience … queue against response and resolution targets. Clear written runbooks and documentation. Useful : Cloudflare Zero Trust and WARP. FlexLM licence administration. SLURM and HPC or EDA compute environments. Semiconductor or engineering environments using Cadence or Synopsys tools. Kubernetes. Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends ...

quality and bring down costs, then this is the role for you. You’ll work closely with colleagues across modelling, system architecture, and RTL design to ensure our RTL releases meet the highest standards of functional quality. That includes contributing to discussions around specification, architecture, and the workflows that … Assertions (SVA) Software fluency in multiple languages Open source tools for silicon development Cocotb (used for all our testbench collateral), Verilator, Icarus Verilog Commercial EDA tools Formal verification Bazel is our chosen tool, familiarity is not expected Contributing to architecture discussions #J-18808-Ljbffr ...