76 to 88 of 88 Electronic Design Automation Jobs in the UK

Collaborate across multiple engineering teams to ensure safety objectives are successfully achieved. Required Skills and Experience :Good understanding of computer architecture and modern SoC design principles. Knowledge of functional safety concepts and standards, particularly ISO 26262.Experience in RTL design of complex ASICs, IPs or SoCs. Experience with safety … Experience with GPU, CPU or other complex processor architectures. Familiarity with verification methodologies including System Verilog, UVM or formal verification. Experience with industry-standard EDA tools (e.g. Cadence or Synopsys).Knowledge of requirements management tools such as Jama, DRM or similar. Exposure to both hardware and software functional safety development. ...

across global sites. In this role, your will oversee the platforms and services that are essential to chip development, including high-performance compute environments, EDA tool infrastructure, job scheduling systems, revision control platforms, enterprise storage, automation, and engineering productivity tooling. The ideal candidate combines deep technical expertise with strong … observabilityDrive operational excellence across 24x7 production environments, including incident response, root cause analysis, change management, and disaster recovery planningPartner with silicon engineering, CAD/EDA teams, IT, security, program management, and executive leadership to align infrastructure priorities with business and product development goalsImprove engineering productivity by advancing automation, self ...

learning, building next‐generation tools to transform how complex integrated circuits are verified. Their technology accelerates simulation coverage and reduces tapeout risk - giving chip design teams a step‐change in capability. This is a high‐impact opportunity for a Machine Learning Engineer looking to make a difference in silicon. … system ownership from data ingestion to model deployment Clear communication - writing specs, documenting APIs, presenting to customers Familiarity with circuit simulation or EDA tools (nice to have) C++/CUDA experience for performance‐critical components (nice to have) Startup or fast‐moving team experience Why consider it: Competitive salary, bonus ...

Limited in Cambridge is seeking an EDA Optimisation Engineer to drive data-driven optimisation, analysis and maintenance of Arm’s engineering platforms. You will help improve system utilisation, efficiency and cost-performance across HPC compute, cloud, Emulation and FPGA environments. In a metrics-first environment, you will develop dashboards, pipelines ...

leading technology firm in Greater London is seeking a highly skilled Senior/Principal Physical Design Engineer to drive the implementation of next-generation chip designs. The successful candidate will work on complex physical designs from synthesis to sign … collaborate with various engineering teams to optimize performance and manufacturability. Ideal candidates have 7+ years experience in physical design and proficiency in EDA tools. This is an exciting opportunity to join a dynamic group innovating in the AI sector. #J-18808-Ljbffr ...

Aion Silicon is seeking a Senior EDA & HPC Infrastructure Engineer to own and evolve the Linux-based EDA compute platform. You will manage licensing, job scheduling, storage and networking with a strong emphasis on AWS cloud engineering. The role is remote with UK working hours, offering full-time permanent employment. ...

join our Solutions Engineering team. You will help ensure power efficiency and performance of our compute solutions and shape design flows and EDA tool integration. You will define UPF specifications, maintain UPF across hierarchical domains, and assess PDN tradeoffs to optimize power and performance. Hybrid working and strong collaboration ...

high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements Modern semiconductor process technologies including 28nm, 14/16nm, 7nm EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop ...

high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements Modern semiconductor process technologies including 28nm, 14/16nm, 7nm EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop ...

Aion Silicon is seeking a Senior EDA & HPC Infrastructure Engineer to own and evolve our Linux-based EDA compute platform and AWS-backed infrastructure. The role combines hands-on Linux system administration with cloud engineering, to ensure performance, licensing stability and scalable compute for engineering workloads. You will manage licence … servers, grid services and production scheduling while driving automation, security and cost control across a global engineering environment. #J-18808-Ljbffr ...

Accelerator grant to develop solutions for frontier applications of integrated photonics. Today we are a team of around 20 people in Cambridge, automating PDK design for integrated photonics and building the hub that connects chip designers, IP providers and foundries. Behind the product sits a serious compute and data …/Beneficial HPC‐style job scheduling (Kueue, Slurm, MPI, or similar). Experience with large scientific or array datasets. Any background in photonics, semiconductors, EDA, or scientific computing. We are particularly interested in people who can solve complex problems, learn quickly and make a meaningful contribution. ...