Staff Analog Mixed-Signal Design and Modelling Engineer
- Location
- Oxford, England, United Kingdom
chip that the whole team simulates against, a mixed‐abstraction model combining transistor‐level circuits with Verilog‐A/Verilog‐AMS and SystemVerilog real‐number behavioural blocks. These models will be derived from first‐principles mathematics and correlated against schematic and measured silicon. You will decide which blocks are represented … production Cadence flow: Virtuoso, Spectre, Xcelium and AMS Designer or similar co‐simulation environments, including parasitic extraction and post‐layout sign‐off SystemVerilog, plus MATLAB or Python/NumPy for analysis and model validation; scripting to automate model generation, checking and regression Cryogenic, space or other extreme‐environment silicon experience ...