2 of 2 SystemVerilog Jobs in the Thames Valley

Master’s degree in Electronic Engineering (or related field) Experience in digital ASIC design and verification, including:Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable skills Experience with formal verification ...

A Senior Verification Engineer will join an exciting Semiconductor Scale-up to undertake digital, mixed signal and analog verification related to high speed Serdes designs. Youll bring 7+ years Verification experience, strong Scripting skills and ...