1 to 25 of 28 SystemVerilog Jobs in the UK excluding London

that are degree qualified (or equivalent) with significant experience in FPGA development. * Competent VHDL Language and Design Skills. * Competent Verification Skills using VHDL and SystemVerilog methodologies * A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs * Experience of professionally configuring and documenting designs * Experience of working ...

software and infrastructure teams to optimise full-stack performance. Requirements: 7+ years FPGA/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Bonus ...

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

software and infrastructure teams to optimise full-stack performance. Requirements: 7 years FPGA/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Bonus ...

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

system architecture and documentation. Skills & Experience Field Programmable Gate Arrays and digital signal processing Proven experience in FPGA design (VHDL/Verilog/SystemVerilog). Strong background in DSP implementation and digital transceiver design. Solid understanding of digital and RF hardware principles. Familiarity with AXI bus architectures and software-controlled ...

challenges. Desirable Skills (Useful but not required - ideal for more experienced applicants) Experience with Vivado, Libero, or additional Quartus tool chains. Knowledge of Verilog, SystemVerilog, or cryptographic algorithms. Exposure to UVM/OSVVM or Assertion Based Verification. Understanding of networking protocols (Layer 2/3), USB 3.2, or NVMe. Background ...

engineering or a related field. At least 3+ years of commercial FPGA and general hardware design experience. Proficient in FPGA design using VHDL/SystemVerilog with AMD (Xilinx), Lattice, or Intel (Altera) products. Familiar with high-speed interfaces and advanced simulation methods. Strong communication skills for effective collaboration with team ...

digital hardware design experience, including 3-5 years in a leadership/management role Strong experience with RTL design (VHDL/Verilog/SystemVerilog), simulation, synthesis, timing analysis, and hardware validation Knowledge of high-speed interfaces, DSP, control logic, and Image Processing Understanding of hardware-software co-design, embedded systems ...

School in Computer Science, Mathematics, Electronic/Electrical Engineering, or other related field. Working experience in digital design. Strong RTL design skills in Verilog, SystemVerilog or VHDL. Analytical thinking and problem solving approach. “Nice To Have” Skills and Experience : Knowledge of computer architecture. Ability to make trade-offs between power ...

high-integrity engineering domains. Strong communication skills and ability to work within structured engineering processes. Technical Knowledge Beneficial to the Role VHDL , Verilog or SystemVerilog for digital design and implementation. Verification testbench architecture using SystemVerilog or C++ . Advanced verification methodologies such as OSVVM , UVVM or advanced VHDL verification techniques. ...

test) Strong background in Digital Signal Processing (DSP) design and optimisation Excellent academic background with a degree from a top university Proficiency in SystemVerilog or VHDL Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location: Cambridge Salary: £70k–£120k + equity ...

verification approaches (e.g., UVM/OSVVM/ABV). Bonus points for: experience with Xilinx/Intel (Altera)/Microchip devices; ModelSim/QuestaSim; SystemVerilog/Verilog; Layer-2/3 networking, USB 3.2 or NVMe; Red Hat Linux; interest in cryptographic systems. Excellent problem-solving, communication, and time-management … Engineer: Design and develop FPGA modules and subsystems across a range of devices and SoC platforms. Create clean, maintainable RTL (VHDL/Verilog/SystemVerilog); build testbenches and validate via simulation and hardware. Integrate FPGA blocks into wider system architectures; collaborate with software, hardware and verification colleagues. Keep pace with ...

offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources ...

runtime performance and improve the debug facility Provide technical support to other teams Preferred Experience Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ...

Bachelor’s, Master's or PhD degree in Electrical Engineering (or related discipline) Comprehensive understanding of digital circuit design in RTL using Verilog and SystemVerilog Knowledge and understanding of verification of block-level digital designs Experience and understanding of synthesis and timing analysis of digital circuits Knowledge of design ...

least 5 years of relevant industry experience Professional membership of an engineering body, ideally chartered or actively working towards Chartered status Testbench development using SystemVerilog or C++ Advanced verification methodologies (VHDL, OSVVM, UVVM) Digital hardware design using VHDL and Verilog/SystemVerilog DESIREABLE: Requirements management tools such as IBM Rational ...

About this Position: We are seeking an experienced Senior/Principal FPGA Engineer to join a dynamic team working on cutting-edge systems within the aerospace and defence industry. This role focuses on designing and ...

Stevenage Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

Bristol Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

Bolton Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPG... ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place …/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/ ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place … AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/ ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place … AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/ ...