1 to 25 of 76 UVM Jobs in the UK excluding London

domain experience or relevant experience in the Aerospace industry Development and certification of airborne equipment New Product Introduction experience Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Qualifications Honours degree or equivalent in Electronics Engineering or another STEM-based subject Current valid More ❯

to deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. More ❯

Desirable Development of real-time, embedded, safety-critical firmware, preferably in accordance with RTCA/DO-254 DAL D Independent verification using SystemVerilog/UVM Relevant experience in the Aerospace or Defence industry Experience of embedded processor cores (e.g. ARM) in FPGA designs Familiarity with latest FPGA device families Qualifications More ❯

Using FPGA technologies especially from either Xilinx, Microsemi (Actel) or Lattice and their tools Advanced verification techniques using either VHDL or System Verilog/UVM Specifying complex timing and area constraints for efficient FPGA place and route Ability to analyse system level requirements and derive detailed Firmware requirements A methodical More ❯

Verilog or SystemVerilog Experience with one or more major FPGA toolchains (Xilinx, Intel, Lattice, etc.) Confident designing testbenches and working with verification methodologies (e.g. UVM, OSVVM, UVVM) Hands-on use of simulation tools (ModelSim, QuestaSim, Vivado) Requirements-led development (e.g. DOORS or structured specs) Comfortable working within secure, safety-critical More ❯

ARM-based designs and/or ARM System Architectures. Familiarity with ARM debugger and trace features e.g ARM DS, DSTREAM. Experience with verification methodologies - UVM/OVM. Knowledge of PCIe and CXL will be a plus. In Return: You will expand your expertise, be challenged and work with advancing technologies. More ❯

solving capabilities. You might also have: Understanding of verification requirements through specification analysis. Experience in GPU/CPU design and associated tools such as UVM or formal verification methodologies. Knowledge of CPU, DSP, or FPU architectures and debugging/testing strategies. Hands-on experience with ASIC, FPGA, and physical design More ❯

hardware verification languages e.g. SystemVerilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM, formal, low power, emulation. Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation More ❯

welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such as csh More ❯

responsibility for resolving issues promptly. DESIRABLE SKILLS: Experience with Vivado, Libero, and Quartus toolchains. Knowledge of Verilog, System Verilog, and cryptographic algorithms. Familiarity with UVM/OSVVM or Assertion Based Verification for design validation. Understanding of Network Layer 2 and Layer 3 protocols, USB 3.2, and NVMe interfaces. Previous experience More ❯

FormalPro Synopsys - Synplify Pro Standards, Frameworks and Techniques Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python The package: You'll receive a very competitive salary (£££ offered depends on level of experience More ❯

FormalPro Synopsys - Synplify Pro Standards, Frameworks and Techniques Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python We're an equal opportunities employer. We're committed to developing a diverse workforce and More ❯

hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation. Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

or hardware verification languages e.g. ( SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

or hardware verification languages e.g. ( SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

or hardware verification languages e.g. ( SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

or hardware verification languages e.g. ( SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

or hardware verification languages e.g. ( SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

in a related subject, with 5+ years of practical experience. Skills & Experience: Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and More ❯

in a related subject, with 5+ years of practical experience. Skills & Experience: Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and More ❯

Our client, a leading company in the Defence & Security sector, is currently seeking an FPGA Engineer to join their team in Luton on a contract basis. This is a fantastic opportunity for an experienced Firmware Engineer to work within an More ❯

Lead FPGA/Firmware Engineer Apply locations GB - Luton - Cap. Green 300 time type Full time posted on Posted 30+ Days Ago job requisition id R Job Description: Would you like to deliver the complex Firmware that forms part of More ❯

level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. More ❯

level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. More ❯

level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. More ❯