Senior Verification Engineer
- Hiring Organisation
- Yoh Solutions Ltd
- Location
- Cambridge, Cambridgeshire, UK
high-quality deliverables and successful project outcomes. Key Responsibilities Develop and execute verification strategies for complex ASIC and FPGA designs. Create and maintain SystemVerilog / UVM verification environments, testbenches and coverage models. Debug RTL and verification issues, ensuring designs meet quality and performance requirements. Collaborate with design, FPGA … engineers and contribute to technical reviews. Essential Skills & Experience Degree in Electronic Engineering, Computer Engineering or a related discipline. Proven experience verifying ASIC and / or FPGA designs. Strong SystemVerilog and UVM expertise. Good understanding of RTL design and digital hardware development. Experience with coverage-driven and assertion-based ...