FPGA Jobs in Cambridgeshire

51 to 54 of 54 FPGA Jobs in Cambridgeshire

Head of Hardware Development

Cambridge, Cambridgeshire, United Kingdom
Hybrid / WFH Options
Ecm Selection
silicon and coding techniques. We are seeking an accomplished Engineering Manager with excellent project and people management skills coupled with a strong technical understanding of high speed electronics and FPGA-based development. To succeed in this role, you will be pragmatic and collaborative by nature, with strong organisational skills and the ability to foster communication between the development teams and … experience to call upon, you naturally prefer a more co-operative approach and value others' input. A solid academic background and strong knowledge of high speed electronics design and FPGA development. Full existing UK work permission. Not essential, but experience within the semiconductor devices industry would be a bonus. The company is driven by success, but moreover by the ability More ❯
Employment Type: Permanent
Salary: GBP Annual
Posted:

DFT Engineer/Architect

Cambridge, Cambridgeshire, United Kingdom
Raspberry Pi
full time basis. The work of the whole ASIC team includes: Architecture, tradeoffs with software/hardware RTL design IP selection and integration Verification at block and system level FPGA platforms for software development and extended verification Implementation including DFT, Synthesis, Place and Route, Timing closure and Signoff checks Package definition and working with assembly partners Validation and characterisation Test More ❯
Employment Type: Permanent
Salary: GBP Annual
Posted:

Test Engineer

Cambridge, England, United Kingdom
IC Resources
hierarchical DFT, scan insertion, and ATPG compression techniques. Create and maintain STA DFT constraints and guide synthesis efforts for optimal test coverage. Collaborate closely with RTL design, IP integration, FPGA development, and physical design teams. Set up and run test pattern generation (ATPG) and debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level More ❯
Posted:

Test Engineer

Ely, England, United Kingdom
IC Resources
hierarchical DFT, scan insertion, and ATPG compression techniques. Create and maintain STA DFT constraints and guide synthesis efforts for optimal test coverage. Collaborate closely with RTL design, IP integration, FPGA development, and physical design teams. Set up and run test pattern generation (ATPG) and debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level More ❯
Posted:
FPGA
Cambridgeshire
25th Percentile
£37,500
Median
£45,000
75th Percentile
£72,000