Senior Staff RTL Design Engineer - CPU Frontend
- Hiring Organisation
- SiFive
- Location
- Cambridge, Cambridgeshire, United Kingdom
- Salary
- £ 70 K
more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.Strong software engineering skills/background, including:Object-oriented, aspect-oriented, and particularly functional programmingTemplated metaprogramming, in any languageCompiler infrastructures, particularly for domain-specific languagesData ...