51 to 72 of 72 ASIC Jobs in the East of England

About the company: We are seeking an experienced ASIC Design Lead, to take ownership of IP and SoC-level design for next-generation semiconductor designs. This role offers the chance to lead a small team, shape verification strategy, and contribute to cutting-edge projects in a fast-paced, collaborative environment. About the role: As the ASIC Design Lead, you will … role suited to someone passionate, motivated by the challenges of building something from the ground up in a start-up environment. What you will be doing: Define and execute ASIC plans for IP/SoC designs Drive functional coverage, assertions, and bug resolution Collaborate with design, architecture, and software teams Mentor junior engineers and guide verification best practices Requirements: 6+ More ❯

About the company: We are seeking an experienced ASIC Design Lead, to take ownership of IP and SoC-level design for next-generation semiconductor designs. This role offers the chance to lead a small team, shape verification strategy, and contribute to cutting-edge projects in a fast-paced, collaborative environment. About the role: As the ASIC Design Lead, you will … role suited to someone passionate, motivated by the challenges of building something from the ground up in a start-up environment. What you will be doing: Define and execute ASIC plans for IP/SoC designs Drive functional coverage, assertions, and bug resolution Collaborate with design, architecture, and software teams Mentor junior engineers and guide verification best practices Requirements: 6+ More ❯

About the company: We are seeking an experienced ASIC Design Lead, to take ownership of IP and SoC-level design for next-generation semiconductor designs. This role offers the chance to lead a small team, shape verification strategy, and contribute to cutting-edge projects in a fast-paced, collaborative environment. About the role: As the ASIC Design Lead, you will … role suited to someone passionate, motivated by the challenges of building something from the ground up in a start-up environment. What you will be doing: Define and execute ASIC plans for IP/SoC designs Drive functional coverage, assertions, and bug resolution Collaborate with design, architecture, and software teams Mentor junior engineers and guide verification best practices Requirements: 6+ More ❯

Role: ASIC Verification Engineer Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Contract: Long-Term | Outside IR35 Rate: Competitive/Negotiable About the Company: This is a forward-thinking technology company developing ground-breaking silicon IP solutions that span compute, AI, graphics, memory, communications, and security. These IPs will form the backbone of future innovations across a wide range of … Working On: You’ll collaborate with global engineering teams on the design and development of next-generation silicon IP. The role offers a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques … Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL or Vulkan APIs is a plus Why Consider This Role? Join high-impact, cutting-edge projects Work within a collaborative, world-class team Flexible working environment – hybrid preferred, remote considered Long-term engagement with potential for extensions More ❯

Role: ASIC Verification Engineer Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Contract: Long-Term | Outside IR35 Rate: Competitive/Negotiable About the Company: This is a forward-thinking technology company developing ground-breaking silicon IP solutions that span compute, AI, graphics, memory, communications, and security. These IPs will form the backbone of future innovations across a wide range of … Working On: You’ll collaborate with global engineering teams on the design and development of next-generation silicon IP. The role offers a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques … Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL or Vulkan APIs is a plus Why Consider This Role? Join high-impact, cutting-edge projects Work within a collaborative, world-class team Flexible working environment – hybrid preferred, remote considered Long-term engagement with potential for extensions More ❯

Social network you want to login/join with: ASIC Design Lead, watford, hertfordshire col-narrow-left Client: microTECH Global LTD Location: watford, hertfordshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 3 Posted: 06.06.2025 Expiry Date: 21.07.2025 col-wide Job Description: About the company: We are seeking an experienced ASIC Design Lead … role offers the chance to lead a small team, shape verification strategy, and contribute to cutting-edge projects in a fast-paced, collaborative environment. About the role: As the ASIC Design Lead, you will be responsible for driving the development and execution of strategies for complex digital IP and SoCs. This is a hands-on and leadership role suited to … someone passionate, motivated by the challenges of building something from the ground up in a start-up environment. What you will be doing: Define and execute ASIC plans for IP/SoC designs Drive functional coverage, assertions, and bug resolution Collaborate with design, architecture, and software teams Mentor junior engineers and guide verification best practices Requirements: 6+ years in digital More ❯

Social network you want to login/join with: ASIC Verification Engineer, watford, hertfordshire col-narrow-left Client: microTECH Global LTD Location: watford, hertfordshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 11 Posted: 06.06.2025 Expiry Date: 21.07.2025 col-wide Job Description: Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Rate: Competitive/… Working On: You’ll collaborate with global engineering teams on the design and development of next-generation silicon IP. The role offers a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Interconnect protocols: AXI More ❯

years' experience in digital IC design and SOC architecture Deep understanding of MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse). Extensive experience with the Digital ASIC Flow, RTL design, and Debug methodologies (e.g., DFT, JTAG, Scan, BIST). Extensive knowledge of SOC architecture, set-up/silicon bring-up, validation and all it's associated processes. More ❯

Have” Skills and Experience : Prior experience with AI/ML, Rich OS or Multimedia applications very desirable Good knowledge of CPU architecture principles and SoC design principles Knowledge of ASIC/SoC design processes In Return: We offer you the opportunity to join a fast-paced team and work with some of the leading tech companies in the world, helping More ❯

Raspberry Pi is seeking an experienced DFT Engineer/Architect to join our innovative ASIC team. The role is based on site in Cambridge with an expectation that the successful candidate comes into the office on a full time basis. The work of the whole ASIC team includes: Architecture, tradeoffs with software/hardware RTL design IP selection and integration More ❯

modern 3D graphics and/or compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape-out, including performance review, analysis More ❯

modern 3D graphics and/or compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape-out, including performance review, analysis More ❯

are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK's Advanced Research Invention Agency (ARIA) is supporting an ambitious programme of work that aims to reduce the the cost of AI by more than 1000x: https … candidate will be able to lead the continued design and implementation of this accelerator, i.e. exploring optimisations at the architectural and microarchitectural levels and pushing the design through the ASIC/EDA tools to generate accurate estimates of performance, power and area (PPA) for inclusion in our simulator framework. Candidates will ideally have worked on complex digital hardware designs and … not particularly relevant for this role. It should be possible to take someone with extensive experience of using FPGA tools and provide them the necessary training to use the ASIC tools. The team at Cambridge consists of three investigators: Prof. Robert Mullins (PI), Prof. Timothy Jones and Dr Rika Antonova, three PhD students and a postdoctoral researcher. The project is More ❯

are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK's Advanced Research Invention Agency (ARIA) is supporting an ambitious programme of work that aims to reduce the the cost of AI by more than 1000x: https … candidate will be able to lead the continued design and implementation of this accelerator, i.e. exploring optimisations at the architectural and microarchitectural levels and pushing the design through the ASIC/EDA tools to generate accurate estimates of performance, power and area (PPA) for inclusion in our simulator framework. Candidates will ideally have worked on complex digital hardware designs and … not particularly relevant for this role. It should be possible to take someone with extensive experience of using FPGA tools and provide them the necessary training to use the ASIC tools. The team at Cambridge consists of three investigators: Prof. Robert Mullins (PI), Prof. Timothy Jones and Dr Rika Antonova, three PhD students and a postdoctoral researcher. The project is More ❯

are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK's Advanced Research Invention Agency (ARIA) is supporting an ambitious programme of work that aims to reduce the the cost of AI by more than 1000x: https … candidate will be able to lead the continued design and implementation of this accelerator, i.e. exploring optimisations at the architectural and microarchitectural levels and pushing the design through the ASIC/EDA tools to generate accurate estimates of performance, power and area (PPA) for inclusion in our simulator framework. Candidates will ideally have worked on complex digital hardware designs and … not particularly relevant for this role. It should be possible to take someone with extensive experience of using FPGA tools and provide them the necessary training to use the ASIC tools. The team at Cambridge consists of three investigators: Prof. Robert Mullins (PI), Prof. Timothy Jones and Dr Rika Antonova, three PhD students and a postdoctoral researcher. The project is More ❯

for the complete design phase including circuit design, implementation and verification of complete sub-systems for sub-6G ICs, as well as also contributing to test plans and ASIC characterisation. The right candidate for the Analog IC Design Engineer role will have: A University degree specialising in Electronics Engineering or similar A well-rounded background within analog IC design More ❯

Senior DFT Engineer – Join a World-Class ASIC Design Team in Cambridge! Are you a seasoned DFT Engineer with a drive for innovation and a passion for silicon design? This is a rare opportunity to join a cutting-edge ASIC team based in Cambridge , renowned for its pioneering work and collaborative approach to product development. As a Senior DFT Engineer … you will work on state-of-the-art ASIC projects, influencing the full design lifecycle while advancing your technical and leadership skills in a dynamic and forward-thinking environment. Role Overview In this role, you'll take the lead in developing and implementing Design-for-Test (DFT) strategies across a wide range of silicon technologies. You’ll work alongside cross … debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level) and BIST integration. Skills: Strong industry experience in DFT architecture , implementation, and verification within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or More ❯

Senior DFT Engineer – Join a World-Class ASIC Design Team in Cambridge! Are you a seasoned DFT Engineer with a drive for innovation and a passion for silicon design? This is a rare opportunity to join a cutting-edge ASIC team based in Cambridge , renowned for its pioneering work and collaborative approach to product development. As a Senior DFT Engineer … you will work on state-of-the-art ASIC projects, influencing the full design lifecycle while advancing your technical and leadership skills in a dynamic and forward-thinking environment. Role Overview In this role, you'll take the lead in developing and implementing Design-for-Test (DFT) strategies across a wide range of silicon technologies. You’ll work alongside cross … debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level) and BIST integration. Skills: Strong industry experience in DFT architecture , implementation, and verification within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or More ❯

Senior DFT Engineer – Join a World-Class ASIC Design Team in Cambridge! Are you a seasoned DFT Engineer with a drive for innovation and a passion for silicon design? This is a rare opportunity to join a cutting-edge ASIC team based in Cambridge , renowned for its pioneering work and collaborative approach to product development. As a Senior DFT Engineer … you will work on state-of-the-art ASIC projects, influencing the full design lifecycle while advancing your technical and leadership skills in a dynamic and forward-thinking environment. Role Overview In this role, you'll take the lead in developing and implementing Design-for-Test (DFT) strategies across a wide range of silicon technologies. You’ll work alongside cross … debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level) and BIST integration. Skills: Strong industry experience in DFT architecture , implementation, and verification within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or More ❯

Senior DFT Engineer – Join a World-Class ASIC Design Team in Cambridge! Are you a seasoned DFT Engineer with a drive for innovation and a passion for silicon design? This is a rare opportunity to join a cutting-edge ASIC team based in Cambridge , renowned for its pioneering work and collaborative approach to product development. As a Senior DFT Engineer … you will work on state-of-the-art ASIC projects, influencing the full design lifecycle while advancing your technical and leadership skills in a dynamic and forward-thinking environment. Role Overview In this role, you'll take the lead in developing and implementing Design-for-Test (DFT) strategies across a wide range of silicon technologies. You’ll work alongside cross … debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level) and BIST integration. Skills: Strong industry experience in DFT architecture , implementation, and verification within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or More ❯

strong understanding of CPU development. Key requirements include: A good degree in Computer Engineering or related field (MSc minimum) A number of years’ solid hands-on experience within Digital ASIC Design and CPU development In-depth knowledge of CPU instruction set architecture and CPU cores Experience within software development and modelling in C Excellent communication skills in English Our client More ❯

compiler software to support GPU products. Writes technical documentation and feature descriptions for GPU projects. Qualifications: Bachelor/Masters degree in Science, Engineering, or related field 3+ years of ASIC design, verification, validation, integration, or related work experience. 1+ years of experience with architecture and design tools. 1+ years of experience with scripting tools and programming languages. 1+ years of More ❯