51 to 75 of 171 ASIC Jobs in England

Yoh, A Day & Zimmermann Company is seeking a Senior Verification Engineer to own UVM-based verification across complex communications IP, taking it from specification through to sign-off. You will work with architects, RTL designers ...

CUDA/Triton/Pallas/CuTe DSL kernel development, lower-level PyTorch/JAX/XLA development, CUDA Graphs, FPGA/ASIC experienceMust have two or more years work experience building deep learning systems, for any domain: robotics, biology, chemistry, physics, audio, video, recommendations, etc.Experience translating methods between areas ...

valuable, but not necessary.Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch/JAX development, intermediate C++, FPGA/ASIC experience, HPC experience.The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base ...

head an FPGA/digital design team focused on space-based 5G communications. You will own technical direction and drive high‐performance FPGA/ASIC delivery, working with cross‐functional teams to translate requirements into robust hardware solutions. The role blends hands-on engineering with team leadership, mentoring engineers ...

Engineer to focus on the verification of microprocessor IP features. This role involves collaboration with diverse teams and requires proficiency in C++, debugging, and ASIC verification. The ideal candidate possesses a Bachelors or Masters degree in Electrical Engineering and at least 3 years of relevant experience. Join AMD in creating ...

seeking a Principal Design Team Leader to steer the hardware design of 5G base station and space-qualified IP. You will guide RTL/ASIC/FPGA development, drive delivery, and ensure robust verification, with a focus on power efficiency and performance. The role requires hands-on leadership, collaboration with ...

have: A degree in Electrical/Electronic Engineering, Computer Engineering or a related discipline Strong hands-on experience in Physical Design for complex ASIC or CPU/SoC designs Experience across the full implementation flow including floorplanning, place and route, CTS and physical sign-off Familiarity with industry-standard ...

metrics Craft automated verification flows What You Bring to The Table Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate-level simulation, etc.) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear ...

metrics Craft automated verification flows What You Bring to The Table Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate-level simulation, etc.) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear ...

report verification metricsCraft automated verification flowsWhat You Bring to The TableCommercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate-level simulation, etc.)Knowledge of verifying CPU architectures or other IPFluency and the ability to write clear and concise ...

metrics Craft automated verification flows What You Bring to The Table Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate-level simulation, etc.) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear ...

optimizing hardware modules, and mentoring junior engineers. Candidates should possess strong digital circuit design skills, experience with RTL design, and familiarity with ASIC or FPGA tools. Joining this innovative team means contributing to technology that positively impacts millions globally. #J-18808-Ljbffr ...

chip technology ecosystem, combined with the commercial skills to identify opportunities, build relationships and drive growth. You may come from a background in ASIC design, semiconductor manufacturing, chip design, electronics, silicon technology, engineering services or semiconductor sales/business development. Key Responsibilities: Develop and execute business development strategies aligned with ...

will shape system-level designs bridging ASICs, SerDes, and photonics across packaging and interconnects. The role requires deep expertise in high‐speed SerDes, ASIC architectures, and optical systems, with cross‐functional collaboration to deliver high-bandwidth, low-power interconnects. #J-18808-Ljbffr ...

Stealth Startup - Deep Tech is seeking a senior specialist to collaborate on the manufacturing, design and implementation of a photonics chip architecture. You will shape all components of the chip, contributing to laser cavities, epitaxy ...

A leading technology firm in Greater London is seeking a highly skilled Senior/Principal Physical Design Engineer to drive the implementation of next-generation chip designs. The successful candidate will work on complex physical ...

looking for Physical Design (PD) and Static Timing Analysis (STA) Engineers . Key Responsibilities Perform Static Timing Analysis (STA) for advanced-node ASIC/SoC designs. Drive timing closure across multiple design stages and operating corners. Analyze and resolve setup and hold timing violations. Perform timing analysis across multiple ...

electrical and optical domains, focusing on SerDes‐based links, photonics integration, and advanced packaging. The role requires a deep background in high‐speed SerDes, ASIC/SoC architectures, and optical systems, with cross‐functional collaboration across semiconductor, photonics, and packaging teams. #J-18808-Ljbffr ...

Raspberry Pi Foundation is seeking an IC Verification engineer to join our ASIC team in Cambridge. You will own IP and chip‐level verification planning and execution, coordinating with design to ensure robust silicon from specs through to sign‐off. The role involves building test benches, debugging complex failures ...

OLIX is seeking an Architect/Staff Embedded Software Engineer to lead hardware‐software integration for the DX‐1 accelerator, spanning ASIC, BMC, and photonic interconnect fabric from pre‐silicon through sustainment. You will shape architectural standards and own critical decisions, partner with the Director of Software Engineering, mentor engineers ...

floorplanning, CTS, place-and-route and sign-off, plus scripting in TCL, Python, or Perl to enhance flows and automation. A strong background in ASIC/CPU/SoC physical design is essential. #J-18808-Ljbffr ...

deliver accurate, verified designs within project timescales. Desirable CMOS Readout IC (ROIC) experience. Imaging IC or image sensor design. Infrared detector electronics. Semiconductor, ASIC or mixed-signal design experience. If you are an experienced Analogue IC Design Engineer looking for a challenging opportunity within aerospace and defence, we would like ...

deliver accurate, verified designs within project timescales. Desirable CMOS Readout IC (ROIC) experience. Imaging IC or image sensor design. Infrared detector electronics. Semiconductor, ASIC or mixed-signal design experience. If you are an experienced Analogue IC Design Engineer looking for a challenging opportunity within aerospace and defence, we would like ...

desire to transition to the manager stream. Significant commercial experience with a variety of functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, coverage collection, gate level simulation, etc.). Knowledge of verifying CPU architectures or other complex IPs (GPUs, NNAs). Proven ability to manage ...

desire to transition to the manager stream.Significant commercial experience with a variety of functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, coverage collection, gate level simulation, etc.).Knowledge of verifying CPU architectures or other complex IPs (GPUs, NNAs).Proven ability to manage workload effectively ...