51 to 62 of 62 ASIC Jobs in England

Technology and Solution IP Group at AMD is adding to the Data Centre design team in Belfast. We focus on design and verification of ASIC blocks for next generation data center networking, focusing on the needs of AI clusters for training and inference; covering the entire design cycle across: architecture … scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency using ASIC and/or FPGA simulation and synthesis tools Familiarity with best practice chip-level verification techniques and languages Experience with Cache Coherency verification would ...

Technology and Solution IP Group at AMD is adding to the Data Centre design team in Belfast. We focus on design and verification of ASIC blocks for next generation data center networking, focusing on the needs of AI clusters for training and inference; covering the entire design cycle across: architecture … scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency using ASIC and/or FPGA simulation and synthesis tools Familiarity with best practice chip-level verification techniques and languages Experience with Cache Coherency verification would ...

Technology and Solution IP Group at AMD is adding to the Data Centre design team in Belfast. We focus on design and verification of ASIC blocks for next generation data center networking, focusing on the needs of AI clusters for training and inference; covering the entire design cycle across: architecture … scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency using ASIC and/or FPGA simulation and synthesis tools Familiarity with best practice chip-level verification techniques and languages Experience with Cache Coherency verification would ...

Senior Design Verification Engineer (FPGA/ASIC) My client, an HFT firm, is seeking a Senior Design Verification Engineer to work on high-performance FPGA and ASIC systems used in ultra-low-latency, real-time environments. Key responsibilities: Develop testbenches, tests, and verification environments for FPGA/ASIC designs Create … Manage test suites, coverage, and CI infrastructure Contribute to internal tools and open-source verification projects Key requirements: 3+ years’ experience in FPGA or ASIC functional verification Strong SystemVerilog skills (UVM or similar frameworks) Experience with functional and code coverage Proficiency in Python ; C++ a plus Comfortable working ...

Digital Verification Engineer with a strong Semiconductor background involving the verification of complex designs (FPGA or ASIC) and with some UVM experience is sought by an exciting new name in the Semiconductor industry. Competitive salary plus Hybrid working and good benefits. Rewarding opportunity for a Digital Verification Engineer seeking … experience of working within the semiconductor industry. Industrial experience of digital verification with some UVM experience. Track record of verifying complex designs (FPGA/ASIC) ideally in high volume applications. Scripting skills. Good knowledge of simulation tools and debugging techniques. Good knowledge of Metrics-driven verification. Understanding of restrained random ...

Digital Verification Engineer with a strong Semiconductor background involving the verification of complex designs (FPGA or ASIC) and with some UVM experience is sought by an exciting new name in the Semiconductor industry. Competitive salary plus Hybrid working and good benefits. Rewarding opportunity for a Digital Verification Engineer seeking … experience of working within the semiconductor industry. Industrial experience of digital verification with some UVM experience. Track record of verifying complex designs (FPGA/ASIC) ideally in high volume applications. Scripting skills. Good knowledge of simulation tools and debugging techniques. Good knowledge of Metrics-driven verification. Understanding of restrained random ...

Overview: My client is a global tech firm seeking an FPGA/ASIC Hardware Engineer to design high-performance, low-latency compute systems. You’ll design RTL in SystemVerilog, optimise data pipelines, and work on advanced hardware platforms in a hands-on, performance-focused role—no industry background required. … responsibilities: Design and develop FPGA and/or ASIC solutions as part of a cross-functional engineering team Implement and optimise RTL for complex data structures and processing pipelines Explore and evaluate new tools, technologies, and architectures Contribute to a fast-moving, modern hardware development environment Key requirements: 4+ years ...

opportunity to shape next-generation digital ICs used in safety-critical and high-performance applications. You’ll lead the digital development activity across complex ASIC and MCU products, combining hands-on technical oversight with team leadership, project delivery and cross-functional collaboration across global engineering teams. The Role This position … Experience Essential: Degree-qualified (BEng or MEng) in Electronics, Engineering or a related discipline 5+ years’ experience in digital or mixed-signal IC design (ASIC preferred) Proven experience leading or managing engineers or technical projects Strong knowledge of the full digital IC design lifecycle from specification to silicon Experience with ...

Senior Digital ASIC Design Engineer - Bristol or Romsey A leading semiconductor company is growing its advanced R&D function and is seeking a Senior Digital ASIC Design Engineer to support the development of next-generation mixed-signal devices used in high-performance data applications. As a Senior Digital ASIC Design … sign-off and production quality standards Sharing knowledge and supporting the development of junior engineers Key experience includes: A strong track record of delivering ASIC designs from concept to silicon Advanced RTL design skills in Verilog or VHDL Experience with low-power digital design techniques Familiarity with industry-standard synthesis ...

exciting opportunity is available for a CPU ASIC Design Engineer to join a global industry leader at their largest UK office, based in Cambridge. You will join a highly respected engineering team working on next-generation products, including high-performance CPUs and GPUs, ultra-low-power IoT devices, and advanced … wearables. As a CPU ASIC Engineer, you will focus on CPU RTL development for high-performance, low-power systems. Working closely with chip architects, you will help define micro-architectures and contribute to early architectural and product-level decisions throughout the development lifecycle. Responsibilities Collaborate with the CPU modelling team ...

Required experience Proven professional experience in one or more of the following areas: Implementation of modern decoding or signal-processing algorithms on FPGA or ASIC SoC architecture involving CPUs and custom hardware accelerators Large-scale, complex FPGA or ASIC-based systems Experience with modern FPGA platforms Strong capability in testing … debugging, and improving complex digital systems Ability to translate high-level product requirements into clear technical specifications Experience working in ASIC design environments (sub-48nm process nodes) On offer is a comprehensive benefits package which includes equity, base and bonus as well as private medical and various insurances. Visa sponsorship ...

Senior Physical Design Engineer - Farnborough A leading international space technology organisation is continuing to expand its advanced ASIC capability and is seeking a Senior Physical Design Engineer to support the development of complex satellite SoCs. This opportunity sits within our client’s semiconductor division, focused on high-performance communication devices … functional engineering teams and external partners to optimise flow and delivery Skills and experience required: Strong background as a Senior Physical Design Engineer within ASIC development Proven experience across advanced node physical design flows (28nm or below preferred) Solid understanding of synthesis, floorplanning, P&R, CTS, STA, timing closure ...