26 to 50 of 195 ASIC Jobs in the UK

have a Senior R&D position which focusses on HW-SW co-design & architecture. You will be part of key R&D projects for complex CPU architecture requirements for ASIC SOCs and IP. Offering excellent salary, circa £100k - dependent on years and relevance of experience Must have skills: University degree - BSc/MSc/PhD in Electronics, Microelectronics, Physics or … C/C++/System C Bonus/"nice-to-have" skills: Industry experience in RTL design/RTL coding/digital design/hardware design - for FPGA/ASIC (VHDL and/or Verilog, System verilog) Digital Verification (UVM/system verilog) OR Formal verification methods - Jasper Gold, C/system C Definition of complex architecture High-speed digital More ❯

Position: ASIC Verification Engineer Location: Oxfordshire, UK Full time/Perm: Office based & hybrid working arrangement with the option to work from home on Monday and Fridays. About the Client: My client is one of the leading providers of high-performance client, data centre and enterprise solid-state storage products that enables customers to tackle storage challenges head on while … today's data-driven era. I am looking for a proactive, delivery focused individual to contribute to time critical projects in this role, you will work closely with other ASIC team members, as well as with cross functional teams including architecture, firmware and validation. Essential qualifications and skills: - Bachelor or Master's degree in Electronic Engineering or related field - 12+ … years of digital ASIC verification experience - Practical experience and understanding of: - Requirement capture, verification planning and coverage closure - System Verilog and UVM test benches - Creation of UVM test benches - System Verilog assertions - Managing regression and debugging failures - Scripting languages (e.g. Perl/Python/TCL) - Team player with good oral and written communication skills Desirable skills: - Team leadership skills - Familiarity More ❯

for deployment onboard satellites. They are looking to appoint a Lead FPGA Design Engineer to take a central role in shaping and delivering complex RTL designs for FPGA (and ASIC) targets. This is a senior, hands-on role where technical excellence and delivery ownership go hand in hand. The successful candidate will lead key projects, mentor junior engineers, and drive … both product direction and engineering methodology. What they’re looking for: Extensive experience developing complex digital designs in Verilog or SystemVerilog Strong track record delivering high-throughput FPGA or ASIC IP, ideally in signal processing or comms applications Expertise in simulation, synthesis, timing optimisation, and lab-based validation Proficiency with industry-standard EDA tools and UVM-based verification Ability to More ❯

A skilled communicator and collaborator, you thrive in a fast-paced, innovative environment. Required Skills: Expertise in digital IC design and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/ More ❯

A skilled communicator and collaborator, you thrive in a fast-paced, innovative environment. Required Skills: Expertise in digital IC design and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/ More ❯

A skilled communicator and collaborator, you thrive in a fast-paced, innovative environment. Required Skills: Expertise in digital IC design and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/ More ❯

throughput and capacity of emerging FPGA technologies. Work closely with cross-functional teams, including Quantitative Research, Engineering, and Traders. Skill Set Requirements: Minimum 2 years experience in the full ASIC or FPGA design life cycle, including hardware architecture, RTL coding, simulation, verification, system integration, and testing. Experience working in Verilog, System Verilog, and either Python or C++. Strong working knowledge More ❯

mission is to create through constant innovation the best-in-class GPUs for a wide range of market segments and applications. This is an excellent opportunity to take your ASIC design verification career to a whole new level on cutting-edge designs within our Power VR Hardware Graphics group. Day to day, you'll take responsibility for applying modern techniques More ❯

analysis of complex issues and resolve them in a timely manner Have excellent knowledge of SystemVerilog and UVM Be able to develop new verification flows Have working knowledge of ASIC design methodologies, flows and tools Be able to plan, estimate and track your own work Experience working on multiple projects at one time The skill to be able to communicate More ❯

Work closely with the exec team to translate product requirements into hardware team deliverables Support discussions with customers during presales and product development Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches Lead AccelerComm's engineering methodology, processes and design techniques Nurture professional growth of team members through regular mentoring, coaching … and feedback Skills, Knowledge & Expertise Essential Skills and Experience: Track record of building and leading high performing collaborative teams Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivery of digital designs for ASIC and FPGA Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience More ❯

to the development of next-generation, commercial-grade LiDAR systems. As the Digital IC Design Engineer you will have experience in digital circuit specification, design, and verification for ASIC and mixed-signal SoCs. This role offers the opportunity to work in a dynamic, startup-style environment where engineers are empowered to take on varied responsibilities and broaden their technical More ❯

us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a ASIC Lead (Digital) who can drive a complex, high‐speed mixed‐signal chip from concept to mass production while line‐managing and mentoring a world‐class team of design engineers. You … serve as the principal technical authority for every digital block that underpins our OTPU. Responsibilities Architect, plan and deliver the digital top level of a multi‐lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical … monitoring, calibration engines and field‐update hooks. Encourage a culture of continuous improvement —methodology automation, design‐flow enhancements, documentation and knowledge sharing. Skills & Experience 12 + years of digital ASIC development, with at least 3 full product cycles taken from specification through volume production. Demonstrated success leading a digital team that delivered high speed ASICs containing high‐speed mixed‐signal More ❯

us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a ASIC Lead (Digital) who can drive a complex, high‐speed mixed‐signal chip from concept to mass production while line‐managing and mentoring a world‐class team of design engineers. You … serve as the principal technical authority for every digital block that underpins our OTPU. Responsibilities Architect, plan and deliver the digital top level of a multi‐lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical … monitoring, calibration engines and field‐update hooks. Encourage a culture of continuous improvement —methodology automation, design‐flow enhancements, documentation and knowledge sharing. Skills & Experience 12 + years of digital ASIC development, with at least 3 full product cycles taken from specification through volume production. Demonstrated success leading a digital team that delivered high speed ASICs containing high‐speed mixed‐signal More ❯

us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a ASIC Lead (Digital) who can drive a complex, high‐speed mixed‐signal chip from concept to mass production while line‐managing and mentoring a world‐class team of design engineers. You … serve as the principal technical authority for every digital block that underpins our OTPU. Responsibilities Architect, plan and deliver the digital top level of a multi‐lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical … monitoring, calibration engines and field‐update hooks. Encourage a culture of continuous improvement —methodology automation, design‐flow enhancements, documentation and knowledge sharing. Skills & Experience 12 + years of digital ASIC development, with at least 3 full product cycles taken from specification through volume production. Demonstrated success leading a digital team that delivered high speed ASICs containing high‐speed mixed‐signal More ❯

automation and proficiency in at least one programming language (C++, Python, TCL etc.). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work More ❯

be involved in evaluating mixed-signal ASICs, prototyping on FPGA, and developing Proof-of-Concept systems. The position offers the opportunity to work closely with advanced hardware platforms, porting ASIC RTL code onto FPGA for pre-silicon testing, designing test benches, and contributing to system-level architecture validation. This is a fantastic opportunity for a System Emulation Engineer who is More ❯

be involved in evaluating mixed-signal ASICs, prototyping on FPGA, and developing Proof-of-Concept systems. The position offers the opportunity to work closely with advanced hardware platforms, porting ASIC RTL code onto FPGA for pre-silicon testing, designing test benches, and contributing to system-level architecture validation. This is a fantastic opportunity for a System Emulation Engineer who is More ❯

that benefits the world in three ways: Enabling Customers, Transforming Industries and Enriching Lives. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work More ❯

leadership to build knowledge and support the team development. Work closely with the exec team to translate product requirements into hardware team deliverables. Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches. Lead engineering methodology, processes and design techniques. Nurture professional growth of team members through regular mentoring, coaching, and feedback … Skills, Knowledge & Expertise: Track record of building and leading high performing collaborative teams. Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products. A strong skillset in delivery of digital designs for ASIC and FPGA. Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and More ❯

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators. These high performance designs require even higher performance verification. We are looking for … rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb. FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing … and continuous integration infrastructure Developing and improving open-source and internal tools Qualifications Superb debug and analytical skills Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional coverage collection/analysis Experience with SystemVerilog and industry-standard frameworks such as UVM Experience with Python Comfortable in a Linux environment Familiarity with Verilator More ❯

Track and report verification metrics Craft automated verification flows What we need Significant commercial experience with a variety of functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate level simulation etc ) Knowledge of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and More ❯

Guide, mentor and coach junior engineers in the team What we need Significant commercial experience with a variety of functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate level simulation etc ) Knowledge of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and More ❯

formal verification, emulation, coverage‐driven flows, RISC‐V vectors, and AI‐centric design techniques to keep Flux at the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and More ❯

formal verification, emulation, coverage‐driven flows, RISC‐V vectors, and AI‐centric design techniques to keep Flux at the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and More ❯

formal verification, emulation, coverage‐driven flows, RISC‐V vectors, and AI‐centric design techniques to keep Flux at the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and More ❯