26 to 50 of 87 Design for Test Jobs in the UK

the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SR. STAFF DFT ENGINEER( TECH LEAD) T HE ROLE : We are seeking a highly experienced DFT engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong … technical background and extensive experience in DFT methodologies, particularly in the context of CPU core design and development. As a DFT engineer in AMD's CPU Cores team, you will have an outstanding opportunity to work on AMD's next-generation CPU core designs. You will work as part of an experienced, skilled, and motivated engineering team with … help make AMD's ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology. As a senior member within the DFT team, you will work closely with the Architecture, Design, Verification, Physical Design teams and Product Engineers to achieve first pass silicon success. THE PERSON: A successful More ❯

speed and highly reliable circuits in accordance with DO-254 if required. Design PCB layouts considering security, EMC and TEMPEST implications and rules. With input from Production Test, incorporate test points in the layout to make the PCB testable without comprising the performance required by hardware engineers. Work with the electronic hardware team to understand circuit … Liaise with bare PCB fabricators and PCB assembly houses, as required, to ensure the design is of high quality and conforms to their stackup, DRC, DFM and DFT requirements. Work with the mechanical engineers to ensure the PCB design is in accordance with their requirements and space envelope. Liaising with the procurement and supply chain teams … Extensive experience of using industry standard toolsets for PCB layout and simulation. In-depth knowledge of routing practices, guidelines and IPC standards. Experience of implementing DFM and DFT features on PCBs and review processes with suppliers. Must have proven experience of using modern design tools with a record of successful PCB designs covering a range of More ❯

speed and highly reliable circuits in accordance with DO-254 if required. Design PCB layouts considering security, EMC and TEMPEST implications and rules. With input from Production Test, incorporate test points in the layout to make the PCB testable without comprising the performance required by hardware engineers. Work with the electronic hardware team to understand circuit … Liaise with bare PCB fabricators and PCB assembly houses, as required, to ensure the design is of high quality and conforms to their stackup, DRC, DFM and DFT requirements. Work with the mechanical engineers to ensure the PCB design is in accordance with their requirements and space envelope. Liaising with the procurement and supply chain teams … Extensive experience of using industry standard toolsets for PCB layout and simulation. In-depth knowledge of routing practices, guidelines and IPC standards. Experience of implementing DFM and DFT features on PCBs and review processes with suppliers. Must have proven experience of using modern design tools with a record of successful PCB designs covering a range of More ❯

that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com. Job Description Summary: The Aiding Technologies Integration & Test Group at Draper is seeking a Principal Integration & Test Engineer with broad technical skills and a wealth of industry experience to lead/advise teams in a multidisciplinary … and advising programs and business areas on the best practices for the development of test plans and procedures, supporting the design and development process (DFT), analysis and evaluation of sensors (custom and COTS) and sensor performance, and the design, manufacture, and implementation of all required supporting test equipment, fixturing, and test … and develop test systems (hardware and software), test equipment, and fixturing required to support integration and testing activities for assigned programs while implementing DFT/DFM and related industry best practices. Demonstrated ability to expertly lead medium to large sized teams, collaborate, and present to stakeholders across internal and external functional boundaries. Proven ability More ❯

Join a trailblazing organisation at the forefront of the new space economy, developing next-generation solutions for satellite communications, deep space missions, and Earth observation. With a growing footprint in the UK and close ties to leading partners across Europe, this is a unique opportunity to contribute to ground-breaking projects that are shaping the future of space … Impact Step into a key engineering role where your work will directly support advanced telecom payloads, scientific instrumentation, and cutting-edge space-based sensors. As a Senior PCB Design Engineer , you'll play a critical role in converting complex system requirements into robust, high-performance printed circuit boards designed for the most demanding environments. Key Responsibilities … speed signal routing, power distribution, and mixed-signal design Familiarity with Design for Manufacturability (DFM) and Design for Testability (DFT) Minimum of 5 years hands-on experience in PCB design for high-reliability applications Excellent communication, problem-solving, and documentation skills Why Join Us? Be part More ❯

Senior Physical Design Engineer – Bristol I am looking for an experienced Physical Design Engineer to join a client in their brand-new IC Design team. This is a fantastic opportunity to join a well-funded start-up developing optical processing technology for high-performance computing. You will join as their … first Physical Design Engineer, giving you the opportunity to take on a varied role and own all Physical Design tasks. Requirements: Bachelor's or Master's degree in Electronics or Electrical Engineering Good understanding of RTL to GDS implementation … flow Experience working at 28nm, 16nm, 14nm, or 7nm process nodes Experience with TCL, Shell, Python, etc. Experience in tapeout procedures Expertise in timing constraints and STA Experience with DFT methodologies For more information on this role or others, please contact Jordan Browne. #J-18808-Ljbffr More ❯

Working for a cutting-edge semiconductor company, I am looking to recruit a SOC Design Architect for fascinating and brand-new project work. The position is available for engineers/applicants who can demonstrate experience of full chip design, (plus understanding/experience of) architecture and delivery (to tape-out … of experience - circa £75-90k, with excellent package and benefits. Based in Cambridgshire, you will be tasked with the end to end SOC architecture of new chips for brand new products in the market. Key skills/requirements: BSc/MSc/PhD in Micro-electronics, physics, or similar filed Approx 5-10 years' experience in digital … understanding of MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse). Extensive experience with the Digital ASIC Flow, RTL design, and Debug methodologies (e.g., DFT, JTAG, Scan, BIST). Extensive knowledge of SOC architecture, set-up/silicon bring-up, validation and all it's associated processes. SOC design, system design More ❯

Job Title: Senior Digital Design Engineer Position: Full time permanent position Location: Bristol Salary Range: 50K - 80K GBP per annum depending on experience Client Information: My client is looking to strengthen their ASIC Digital Design team. Looking for bright candidates who have an enthusiasm and aptitude for working with ASIC chips. Designing … chips for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. You will have a strong academic record, around 7-10 years' experience in industry working on ASIC developments and IP design. If you have at least one successful project as Technical Lead, a more senior position could … understanding of all aspects of ASIC FE design, from specification to RTL, and with a basic understanding of RTL to tape out flow ASIC implementation skills (synthesis, DFT, timing closure) Experience to lead one complex IP design and/or full ASIC design, from specification to full RTL Specific expertise in the following technical More ❯

Job Title: Senior Digital Design Engineer Position: Full time permanent position Location: Bristol Salary Range: 50K – 80K GBP per annum depending on experience Client Information: My client is looking to strengthen their ASIC Digital Design team. Looking for bright candidates who have an enthusiasm and aptitude for working with ASIC chips. Designing … chips for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. You will have a strong academic record, around 7-10 years’ experience in industry working on ASIC developments and IP design. If you have at least one successful project as Technical Lead, a more senior position could … understanding of all aspects of ASIC FE design, from specification to RTL, and with a basic understanding of RTL to tape out flow ASIC implementation skills (synthesis, DFT, timing closure) Experience to lead one complex IP design and/or full ASIC design, from specification to full RTL Specific expertise in the following technical More ❯

Press Tab to Move to Skip to Content Link Select how often (in days) to receive an alert: Create Alert An Amazing Career Opportunity for a Manufacturing Test Engineer! Location: Cardiff, UK Job ID: 39245 HID Global seeks a Senior Manufacturing Test Engineer to be an integral part of the Global PACS ME NPI team. The … a job - it's your chance to join an industry leader to drive innovation in access control and make a real impact on global security solutions. As our Manufacturing Test Engineer, you'll support HID's success by: Drive Alignment on NPI strategy with internal stakeholders and external suppliers. Develop documentation to support production (WRI's, Process flows etc. … with CM's. Process mapping and design. Troubleshoot product functionality as related to tooling and/or process related issues. Assist in the design, fabrication, documentation and test of various electro-mechanical fixtures and test equipment. Coordinate production line set-up and the development of maintenance and calibration procedures. Support Value Analysis/Value Engineering projects More ❯

pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We're backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences Innovations, INKEF Capital and Octopus Ventures, and we … theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology. … providing feedback on the validity of the working principles of a circuit without the assistance of simulation software. Understanding of RF testing and demonstrated experience in the application of DFT of RF blocks. Knowledge of one or more industry-standard EM simulation toolset (ADS, EMX, CDT, HFSS) Strong analytical and problem-solving skills with a high-level of self-management More ❯

Join to apply for the Staff RF IC Design Engineer role at Quantum Motion 1 week ago Be among the first 25 applicants Join to apply for the Staff RF IC Design Engineer role at Quantum Motion Get AI-powered advice on this job and more exclusive features. About The Role And … pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences Innovations, INKEF Capital and Octopus Ventures, and we … providing feedback on the validity of the working principles of a circuit without the assistance of simulation software. Understanding of RF testing and demonstrated experience in the application of DFT of RF blocks. Knowledge of one or more industry-standard EM simulation toolset (ADS, EMX, CDT, HFSS) Strong analytical and problem-solving skills with a high-level of self-management More ❯

OSFP, SFP-DD, etc.) from concept to volume production. Collaborate with design, test, and manufacturing teams to ensure DFM (Design for Manufacturability), DFT (Design for Test), DFR (Design for Reliability), DVT (Design verification) and QT (Qualification testing), are delivered to meet program … milestones. Test stage ownership including methodologies, definition and verification. Produce test specification documents and support test team to deliver key hardware/software/GUI building blocks. Lead integration and verification of test solutions prior to release. Test data review, statistical analysis and results presentation in verification reports. Recommendations for design … NPI engineering. Knowledge of packaging technologies and materials for optical modules. Familiarity with high-speed PCB design, signal integrity, and thermal management. Knowledge of manufacturing test processes and yield analysis. Define and implement test strategies and automation for optical and electrical performance. Develop and execute validation and qualification plans for More ❯

DFT Technical Lead - Digital & SoC Design (CDI) Location: Paris, Caen, or Remote in France Salary: Up to €110,000 Gross per annum + company benefits Join an innovative global semiconductor specialist in high-performance mixed-signal and digital ASICs. They focus on delivering custom system-on-chip (SoC) and transceiver solutions to clients in communications and industrial sectors … leading in advanced technology nodes and silicon-proven design excellence. As a DFT (Design for Test) Technical Leader , you will oversee the design and implementation of DFT architecture for complex SoCs developed in advanced CMOS nodes. You will collaborate with RTL design, physical implementation, and industrialization teams … to ensure efficient testability and high production yield. You will drive test strategies, implement best-in-class DFT flows, and contribute to delivering state-of-the-art transceiver ASICs for various markets. Your responsibilities: Define and drive DFT architecture and implementation for complex SoCs in advanced (sub-20nm) CMOS technologies. Develop and maintain DFT insertion More ❯

Are you an expert in Design for Test (DFT), and we're looking for a talented Principal DFT Engineer to join our dynamic engineering team in Theale/Bristol. This is a unique opportunity to lead critical DFT implementation for cutting-edge ASIC designs while shaping the future of our DFT … practices. As a Principal DFT Engineer, you will take on a leadership role in delivering DFT (including ATPG) implementation at both the chip and block levels. You will lead DFT strategy, manage the implementation of DFT structures, perform formal checks, debug test pattern mismatches, and ensure timing closure in DFT modes. This role may involve acting as an industry … Implementation: Lead the DFT work in projects, including the definition of DFT strategy, implementation of DFT structures, and verification of the DFT structures to meet the project's testability requirements. DFT Expertise: Serve as an expert in DFT tools and techniques, demonstrating advanced skills in tools from Mentor, Synopsys, or Cadence. Complex Problem Solving: Address and resolve complex issues related More ❯

Are you an expert in Design for Test (DFT) , and we're looking for a talented Principal DFT Engineer to join our dynamic engineering team in Theale/Bristol. This is a unique opportunity to lead critical DFT implementation for cutting-edge ASIC designs while shaping the future of our DFT … practices. As a Principal DFT Engineer , you will take on a leadership role in delivering DFT (including ATPG) implementation at both the chip and block levels. You will lead DFT strategy, manage the implementation of DFT structures, perform formal checks, debug test pattern mismatches, and ensure timing closure in DFT modes. This role may involve acting as an industry … Implementation: Lead the DFT work in projects, including the definition of DFT strategy, implementation of DFT structures, and verification of the DFT structures to meet the project's testability requirements. DFT Expertise: Serve as an expert in DFT tools and techniques, demonstrating advanced skills in tools from Mentor, Synopsys, or Cadence. Complex Problem Solving: Address and resolve complex issues related More ❯

Digital Design Engineer Agile Analog is revolutionising the way Analog circuits are designed. We are developing a process agnostic design methodology that uses automation to accelerate the generation of circuits and IP for our customers. Using our innovative technology, we have the capability to design circuits faster, to a higher quality and … physical abstraction of standard cells/IP Knowledge of UPF/CPF for low-power intent specification and implementation Design for Test (DFT) Experience in implementing DFT techniques , including: Scan insertion , scan chain stitching , and test point insertion Built-in Self-Test (BIST) for logic and memory Integration of … Automatic Test Pattern Generation (ATPG) and analyzing test coverage reports Understanding of DFT constraints and impact on design timing and area Tools & Workflow Automation Experienced with industry-standard EDA tools : Synopsys, Cadence, Siemens/Mentor, Xilinx, Intel Proficient in version control systems such as Git for collaborative development Skilled in scripting and workflow automation More ❯

Senior/Principal Physical Design Engineer London - Hybrid Fractile's mission is to enable a new chapter in the AI revolution. We're pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world's largest language models with speed increases of x100. Our team is rapidly expanding, and we're … searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you! We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute … addressing IR drop, electromigration, and low-power design techniques. Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance. Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. Develop flows in EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics More ❯

Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a Digital Design Engineer who is passionate about building and verifying complex, high‐performance ASICs . You will own the definition and execution of verification strategies for … GLS with SDF, and power‐aware checks; work with physical‐design teams on ECOs. Enable post‐silicon bring‐up by generating test vectors, configuring scan/DFT hooks, and supporting FPGA/emulation platforms for firmware and software teams. Mentor junior engineers on verification methodology, code reviews, and best practices; champion continuous‐integration flows, regressions … with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low‐power (UPF/CPF) methodologies. Strong scripting (Python, Tcl, shell) to automate regressions and data analysis. Proven debug skills across RTL, gate‐level and emulation environments. More ❯

Job Title: Hardware Design and Verification Engineer Position: Junior - Mid level Engineers Type: Contract or Permanent Location: Hertfordshire Hybrid Salary Range: Negotiable Client Information: We are building a revolutionary RISC-V-based GPU and AI platform, and we're hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. If you … thrive on innovation and want to work on cutting-edge vector processing and neural compute technologies, this is your opportunity. Design Responsibilities: Architect and implement RTL for critical blocks within our RISC-V vector core GPU Design high-performance, power-efficient compute units for graphics and AI workloads Optimize microarchitecture to meet … accelerator design Familiarity with RISC-V instruction set architecture (preferred) Understanding of graphics pipelines and/or neural network accelerators Awareness of physical design implications (DFT, timing, floorplanning) Proficiency with EDA tools (Synopsys, Cadence, Mentor, etc.) Strong scripting skills in Python, TCL, or similar BS/MS in Electrical Engineering, Computer Engineering, or related field Verification More ❯

Job Title: Digital Design & Verification Engineer - Graduate/JuniorPosition: Graduates & Junior Type: Contract or Permanent Location: Hertfordshire Hybrid Salary Range: Negotiable Client Information: We are building a revolutionary RISC-V-based GPU and AI platform, and we're hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. If you thrive … on innovation and want to work on cutting-edge vector processing and neural compute technologies, this is your opportunity. Design Responsibilities Assist in implementing RTL for key components of our RISC-V vector core GPUContribute to the design of efficient compute units for graphics and AI applications Help refine microarchitectures to meet … vector processors Familiarity with RISC-V ISA is a plus, not a mustUnderstanding of pipelining, memory hierarchies, or parallel compute conceptsInterest in learning physical design fundamentals (timing, DFT, floorplanning)Experience using EDA tools (e.g., Synopsys, Cadence, or similar) during academic or internship projects Scripting knowledge in Python, TCL, or equivalent languagesBS or MS in Electrical Engineering, Computer Engineering More ❯

of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/PCIe/CXL, DDRx/LPDDRx integration verification in SoC RTL. Your key responsibilities will include writing test plans, defining test methodologies, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks … in one or more of various verification methodologies - UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. "Nice To Have" Skills and Experience … Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Power Aware verification techniques Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Experience verifying subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet More ❯

solutions through innovation with uncompromising agility. JOB DESCRIPTION: We commit to build upon the drivers and the productivity tools and enhancement of portfolios and software that supports requirements throughout test workflows. With bigger test coverages and taking measurements, automate the test caveats and collaborate with government agencies as they change their laws and regulations and make designs … to be more secure for the pre-build test executives. A team of seven - Time to market pressure is everything: Areas to cover will include validation and production test systems, take measurements and automate the world around you and expand the capabilities, auto sequencing and parallel testing, electromechanical validation, viewing the data, graphical control coding, software … test automation, multiple test vectors, manage & control complex automation sequences. Our perceive approach is to build out a suite of software architecture with predefined functionalities, software defined instruments and tools that work together across all the ground control engineers' workflows. From the planning, to the configuration, the building of the systems, deploying of the systems, managing the systems More ❯

Based in Reading, Berkshire, our renowned Semiconductor client is recruiting for a Staff Analog RF IC Design Engineer to join their team. With over 700 employees across ten countries, our client is now looking to expand their Reading site. The Staff Analog RF IC Design Engineer will be working as part of a cross … functional team to deliver the next generation products from concept to volume production, taking ownership for the design, implementation and verification of RF/Analog blocks/subsystems up to 10GHz. Responsibilities include: Design, verify and document RF/Analog blocks/subsystems (e.g. LNA, PA, VCO, PLL, mixers, bandgaps, LDO, DC-DC, ADC … and layout Actively contributing to product definition Ensuring that designs follow industry best practice design flows, verification techniques, Design For Test (DFT), isolation, power optimisation etc. The successful candidate will have: A BSc/MSc/PhD degree within Electronic Engineering or similar Established experience in High frequency CMOS RF design More ❯

Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a Digital Design Engineer who is passionate about building and verifying complex, high‐performance ASICs . You will own the definition and execution of verification strategies for … GLS with SDF, and power‐aware checks; work with physical‐design teams on ECOs. Enable post‐silicon bring‐up by generating test vectors, configuring scan/DFT hooks, and supporting FPGA/emulation platforms for firmware and software teams. Mentor junior engineers on verification methodology, code reviews, and best practices; champion continuous‐integration flows, regressions … with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low‐power (UPF/CPF) methodologies. Strong scripting (Python, Tcl, shell) to automate regressions and data analysis. Proven debug skills across RTL, gate‐level and emulation environments. More ❯