Snr FPGA Engineer
- Location
- Oxford, England, United Kingdom
networking equipment. Ensure all FPGA designs achieve required level of timing closure and functional performance before release. Code reviews of existing and new VHDL/Verilog files. Working alongside a team comprising of electronic, mechanical and software design engineers in the creation of high performing and cost-effective solutions. Ensuring … compliance. Full product lifecycle involvement from early conceptual studies through to manufacturing support post-release. Required Skills, Knowledge and Expertise Strong demonstrable experience in VHDL including implementation of algorithms. Verilog experience an advantage. Experience in compilation timing closure is essential. Working knowledge of interface standards such as LVDS, PCIE, GMII ...