226 to 250 of 278 Verilog Jobs in the UK excluding London

Working knowledge of the complete SoC design flow and associated tools and methodologies to deliver working silicon. Experience of RTL and gate-level simulations and related debugging. VHDL/Verilog coding skills. This role can be based in one of several UK locations and visa sponsorship can be provided. For more information, please contact Rachel Mason at IC Resources. More ❯

and refined for a specialised edge. You’ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone far enough. Being More ❯

efficiently Required Skills and Experience: BSc, MSc or PhD degree qualification in Electronics/Computer Engineering or equivalent Ability to understand and use Hardware Description Languages (HDLs) such as Verilog, SystemVerilog or VHDL Strong interest in and understanding of CPU architectures and SoC design principles Experience in using RTL simulation tools for debugging purposes Ability to learn and communicate IP More ❯

Analog Mixed Signal Verification Engineer Job Description: Verification of Mixed-Signal or SoC automotive ASICs Analog/Mixed-Signal self-checking simulation Implementation of analog models in Verilog-/VHDL-AMS to accelerate AMS simulation Application of metric-driven Verification (MDV) methodologies Development and management of Verification plans Integration of Verification IP Measurement and analysis of regression results Collaboration on More ❯

must have: Proven ability to lead teams to deliver complex IP designs, from concept to post-silicon debug. Deep understanding of digital design principles, methodologies and tools. Experience in Verilog/System-Verilog is a must. Knowledge and experience with power analysis at RTL and Gate-Level. Experience of CPU or DSP based design, SoC level design and IP Integration More ❯

Design, prototype, and verify advanced electronic circuits and systems Own schematic capture and PCB layout for digital, analog, and mixed-signal boards Develop embedded systems using FPGAs (VHDL/Verilog), microcontrollers, and SOCs What You’ll Bring Strong experience in schematic design and PCB layout Hands-on expertise in embedded C/Assembler for hardware interfacing Familiarity with PCIe, SPI More ❯

of innovation and with top-tier industry partners. Key Responsibilities: Define digital architectures for AI accelerators, data paths, control logic, and SoC subsystems. Develop high-quality, synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind. Collaborate cross-functionally with verification, physical design, and packaging teams to ensure seamless integration. Leverage Cadence digital tools for synthesis More ❯

server & data center SoC environments. You will also need strong experience with hardware simulation, validation tools, and IO compliance testing. Proficient in high-speed digital design, hardware description languages (Verilog/VHDL), and digital logic design. In-depth understanding of server-grade SoC architectures and the specific requirements of data center applications. Outstanding analytical, troubleshooting, and problem-solving skills. “Nice More ❯

server & data center SoC environments. You will also need strong experience with hardware simulation, validation tools, and IO compliance testing. Proficient in high-speed digital design, hardware description languages (Verilog/VHDL), and digital logic design. In-depth understanding of server-grade SoC architectures and the specific requirements of data center applications. Outstanding analytical, troubleshooting, and problem-solving skills. “Nice More ❯

player Ability to work across teams and programming languages Desirable Experience in the technical specification of complex silicon SoC devices Experience of machine learning or massively parallel computing systems Verilog Low-level software experience Knowledge of one or more of DDR, PCIe, Ethernet, on-chip networks Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual More ❯

Senior Digital Hardware Engineer required to apply their experience in a new and challenging environment, working across the full development life-cycle. Typical tasks include: Analysis of customer requirements. Create & modify electronic designs and architecture. Use simulation tools to generate More ❯

Senior Digital Hardware Engineer required to apply their experience in a new and challenging environment, working across the full development life-cycle. Typical tasks include: Analysis of customer requirements. Create & modify electronic designs and architecture. Use simulation tools to generate More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯