26 to 33 of 33 Tcl Jobs

physical verification tools (e.g. Synopsys/Cadence). Understanding of constraints, timing signoff methodology and advanced-node challenges. Familiarity with scripting (Python, Perl, Tcl, etc.) to support automation. Experience collaborating with global, multi-disciplinary design teams. Email - jordan.browne@ic-resources.com Tel - 01189073075 LinkedIn - https://www.linkedin.com/in/ ...

physical design teams to debug timing paths, root-cause violations and propose practical solutions. Automate flows and enhance STA-related infrastructure using scripting (TCL/Python/Perl). Evaluate timing approaches, methodologies and tool behaviour across new processes and libraries. Partner with central methodology specialists to influence timing strategy ...

understanding of query executions across databases. Hands-on working experience in executing and debugging SQL queries in live environments. Familiar with DML, DDL, DCL, TCL statements and their appropriate usage. Well-versed in database-related issue handling, including deadlocks, slow query troubleshooting, and monitoring. Cloud Understanding: Awareness of cloud architecture ...

work with tool vendors to address any power-related tool or flow issues. Hands-on skills in one of the scripting languages, Shell/TCL/Perl/Python. Javier Leon removed ...

Vivado, Quartus or Libero) and version control (GIT/SVN/CVS). For experienced candidates: proven end-to-end FPGA delivery, interface definition, TCL scripting, and robust verification approaches (e.g., UVM/OSVVM/ABV). Bonus points for: experience with Xilinx/Intel (Altera)/Microchip devices; ModelSim …/Graduate Hardware Engineer/Electronics Engineer/VHDL/Verilog/SystemVerilog/Vivado/Quartus/Libero/ModelSim/QuestaSim/TCL/Xilinx/Intel (Altera)/Microchip (Microsemi)/UVM/OSVVM/Assertion-Based Verification/USB 3.2/NVMe/Layer-2/ ...

role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows.Key ResponsibilitiesDesign high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoCDeliver synthesis-ready RTL meeting timing … integration requirementsImplement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocksDrive timing closure using Vivado toolchainsDevelop automation using Python/Tcl scriptingCollaborate with hardware, SoC, firmware and integration teamsEssential SkillsStrong SystemVerilog RTL design experienceFPGA/Adaptive SoC design flow: synthesis, P&R, timing closureHigh-speed digital interfaces: 100GbE/ ...

role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting … integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration teams Essential Skills Strong SystemVerilog RTL design experience FPGA/Adaptive SoC design flow: synthesis ...

role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration teams Essential Skills Strong SystemVerilog RTL design experience FPGA/Adaptive SoC design flow: synthesis ...