Design Verification Engineer
- Hiring Organisation
- Intellectual Capital Resources
- Location
- Reading, Berkshire, United Kingdom
- Salary
- £ 70 K
ASIC/SoC verification lifecycle, with real ownership of the verification of complex digital subsystems and mixed-signal ICs. Your work will include: Developing SystemVerilog/UVM verification environments Verification planning and test development Constrained-random and coverage-driven verification SVA/assertions Functional and code coverage RTL and testbench … senior levels What they're looking for You'll ideally have a background in ASIC, SoC or Digital IC Verification, with strong experience in: SystemVerilog | UVM | SVA | Constrained Random Verification | Functional Coverage | RTL Debug Experience with mixed-signal verification, formal verification, UPF/low-power verification, gate-level simulation ...