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26 to 29 of 29 SystemVerilog Jobs in Cambridgeshire
Cambridge, south west england, United Kingdom IC Resources
with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design languages such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience with assertions (e.g., SVA - SystemVerilog Assertions More ❯
Cambridge, England, United Kingdom Hybrid / WFH Options European Tech Recruit
higher for Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are … offer a fantastic referral scheme which I would be happy to discuss. Keywords: Semiconductors/Verification/CPU/RTL/IP Level/ SystemVerilog/C++ #semiconductors #verification #cpu #rtl #ip #systemverilog By applying to this role you understand that we may collect your personal data and store and More ❯
cambridge, east anglia, United Kingdom Hybrid / WFH Options European Tech Recruit
higher for Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are … offer a fantastic referral scheme which I would be happy to discuss. Keywords: Semiconductors/Verification/CPU/RTL/IP Level/ SystemVerilog/C++ #semiconductors #verification #cpu #rtl #ip #systemverilog By applying to this role you understand that we may collect your personal data and store and More ❯
Cambridge, south west england, United Kingdom Hybrid / WFH Options European Tech Recruit
higher for Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are … offer a fantastic referral scheme which I would be happy to discuss. Keywords: Semiconductors/Verification/CPU/RTL/IP Level/ SystemVerilog/C++ #semiconductors #verification #cpu #rtl #ip #systemverilog By applying to this role you understand that we may collect your personal data and store and More ❯
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