6 of 6 UVM Jobs in Cambridgeshire

tape-out, including performance review, analysis, costing, and optimisation Understanding of the product's design & verification needs, standardisation, adherence to frameworks and methodolgies e.g. UVM Excellent communicator, with a keen interest in team collaboration and a clear approach to the design & development process Bonus/\"Nice-to-have\" skills Digital ...

Address translation/MMU Experience with random instruction sequencing (RIS) Proven ability to verify designs at block, subsystem, and chip level Proficiency in SystemVerilog, UVM, assertions, and coverage-driven verification Desirable Experience leading or mentoring verification engineers Exposure to formal verification and/or post-silicon bring-up Familiarity with ...

Formal Proof Tools. Familiarity with Formal Verification, Assertions, and Silicon bring-up. Keywords: CPU Verification/Design Verification/DV/SystemVerilog/UVM/Cache Coherence/Branch Prediction/Formal Verification/RIS/SOC/Assembly/Cambridge/Silicon Bring-up If you are interested ...

Collaborates with the design team to understand and define verification requirements for security features Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology Executes test plans and verifies the correctness of hardware security features Works closely with the cross-functional teams to ensure the implementation meets design … Master's degree in Electrical Engineering, Computer Engineering, or a related field Strong understanding of hardware verification methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity with security features and protocols, such as CHERI, is a plus Excellent communication skills and the ability ...

support the high-speed networking function within the engineering team. The focus of the role will be on building and maintaining sophisticated, class-based UVM verification environments, driving coverage closure, and supporting SoC-level integration. This role involves close collaboration with design, architecture, software and systems teams to deliver production … ready silicon for demanding networking applications. Key Responsibilities Verify high-speed connectivity IP using advanced SystemVerilog UVM methodologies. Develop constrained-random test environments and execute comprehensive verification plans. Define test plans and drive functional and code coverage to verification sign-off. Integrate and configure verification IP (VIP) for industry-standard ...

Design Verification Engineer - CPU DV/Microprocessor Verification/SystemVerilog/UVM We are partnered with a global semiconductor company with a major engineering presence in Cambridge. They are looking for a CPU Design Verification Engineer to work on high performance CPU and SoC products across a broad range ...