26 to 35 of 35 Electronic Design Automation Jobs in London

suit someone with a strong background in the following areas and the ability to flexibly apply and combine them on a daily basis: practical electronics test and measurement, experimental design, statistics and data analysis, analogue and mixed-signal circuit operation principles, and CMOS device physics and process. No background in quantum physics is required. Our Team Since 2021 our … who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences Innovations, INKEF Capital and Octopus Ventures … circuit designs through full product test lifecycle: pre-silicon test planning; bring-up and optimisation; inter-die variability studies; and product support (where required) High-quality documentation of experimental design, measurement data, analysis, and conclusions at each step Develop efficient and automated measurement and analysis routines to provide rapid and standardised feedback on new IC designs, driving faster design More ❯

team that thrives on delivering impact and innovation at speed. The role We are seeking highly skilled and motivated Senior/Staff Analog Engineers with expertise in CMOS analog design to lead the design, validation, and implementation of high-performance analog circuits for our next-generation OTPUs. This role demands deep knowledge of CMOS analog circuit design … ideal candidate will have a strong background in electrical engineering and semiconductor physics and a passion for developing reliable, high-performance analog circuits that drive breakthrough AI hardware. Responsibilities Design and develop advanced CMOS analog integrated circuits, including schematic creation, simulation, layout, and testing to meet the performance targets of our OTPU systems. Collaborate closely with cross-functional teams … of industry experience in CMOS integrated circuit design, focusing on analog circuit development. Expertise in analog circuit simulation, schematic capture, layout design, and testing using industry-standard EDA tools. Bachelor’s degree in Electrical Engineering or a related field; an advanced degree is a plus. Strong problem-solving abilities with a keen eye for performance optimisation and noise More ❯

thrives on delivering impact and innovation at speed. The role We are seeking highly skilled and motivated Senior/Staff/Principal Analogue Engineers with expertise in CMOS analogue design to lead the design, validation, and implementation of high-performance analogue circuits for our next-generation OTPUs. This role demands deep knowledge of CMOS analogue circuit design … ideal candidate will have a strong background in electrical engineering and semiconductor physics and a passion for developing reliable, high-performance analogue circuits that drive breakthrough AI hardware. Responsibilities Design and develop advanced CMOS analogue integrated circuits, including schematic creation, simulation, layout, and testing to meet the performance targets of our OTPU systems. Collaborate closely with cross-functional teams … of industry experience in CMOS integrated circuit design, focusing on analogue circuit development. Expertise in analogue circuit simulation, schematic capture, layout design, and testing using industry-standard EDA tools. Bachelor’s degree in Electrical Engineering or a related field; an advanced degree is a plus. Strong problem-solving abilities with a keen eye for performance optimisation and noise More ❯

highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We are seeking highly skilled and motivated Senior/Staff/Principal Digital Design Engineers with a strong focus on CMOS digital design to take end‐to‐end ownership of high‐speed, real‐time data‐processing silicon —from early algorithm modelling to … will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, high-performance digital circuits that drive breakthrough AI hardware. Responsibilities Architect, design and implement high‐throughput digital pipelines (multi‐GSPS input rate, continuous streaming data paths, deep pipelining and hand‐shaking) in advanced CMOS nodes. Prototype and iterate rapidly in FPGA … on multi‐hundred‐MHz to multi‐GHz clock domains and integrating high‐speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar). Expertise with industry‐standard EDA flows: RTL synthesis, CDC/RDC, STA, power‐intent (UPF/CPF), lint, and gate‐level simulation. Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the More ❯

of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The Role We’re searching for a Senior/Staff/Principal Analog Design Engineer with a strong focus on CMOS phase‐locked loops (PLLs) and clock‐distribution networks. You will architect, design and bring to production an ultra‐low‐jitter clocking … loop filters, de‐skew circuits and high‐integrity clock‐tree distribution—all while meeting stringent power, spur and phase‐noise budgets required by next‐generation AI workloads. Responsibilities Architect, design and verify wide‐bandwidth fractional‐N PLLs (multi‐GHz output) including VCOs, charge pumps, loop filters and frequency dividers to achieve sub‐100fsrms integrated jitter. Develop clock‐distribution networks … monitoring. Skills & Experience 7+years of industry experience designing production CMOS PLLs, CDRs or other precision clock generators. Demonstrated success achieving sub‐100fsrms jitter and Mastery of analog/RF EDA tools for schematic capture, SPICE‐/S‐parameter simulation, layout, parasitic extraction and mixed‐signal verification. Bachelor’s degree in Electrical Engineering (or related); Master’s/PhD preferred. Excellent More ❯

of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The Role We’re searching for a Senior/Staff/Principal Analog Design Engineer to architect, design and bring to production ultra‐high‐speed (>20GHz analog bandwidth, >40GS/s) CMOS ADCs and DACs that directly interface with our optical compute … with a passion for developing reliable, high-performance analogue circuits that drive breakthrough AI hardware. Responsibilities Define converter architectures that will deliver on the target of Analog bandwidth>20GHz. Design critical high‐speed building blocks: bootstrapped or switch‐linearised T/H, low‐skew clock trees ( Model and close performance using transistor‐level and behavioural co‐simulation (SpectreRF/… analog bandwidth. Deep knowledge of track‐and‐hold linearity, aperture‐jitter minimisation, current‐steering DAC glitch energy reduction, capacitor and device matching, and metastability‐hard comparators. Proficiency with industry EDA flows: Cadence Virtuoso, SpectreRF/AFS RF, Verilog‐A/AMS, EMX/HFSS for package + on‐chip inductor modelling, and mixed‐signal verification. Demonstrated ability to achieve Experience More ❯

strategic, execution-focused professionals with experience in B2B tech, developer tools, or embedded systems. Location: London preferred Compensation: Competitive salary + equity Experience: - Relevant technical degree, or equivalent, in electronic … engineering. - Proven experience in enterprise sales within automotive, defence or medical companies. - Hands-on sales and used to a start-up environment. - Experience selling embedded tools, developer tools or EDA software into OEMs. 👉 Apply now to Rebecca at IC Resources and help reimagine the infrastructure powering the electronics of tomorrow. More ❯

strategic, execution-focused professionals with experience in B2B tech, developer tools, or embedded systems. Location: London preferred Compensation: Competitive salary + equity Experience: - Relevant technical degree, or equivalent, in electronic … engineering. - Proven experience in enterprise sales within automotive, defence or medical companies. - Hands-on sales and used to a start-up environment. - Experience selling embedded tools, developer tools or EDA software into OEMs. 👉 Apply now to Rebecca at IC Resources and help reimagine the infrastructure powering the electronics of tomorrow. More ❯

people leadership and disciplined program management—all exercised across multiple concurrent tape‐outs. Responsibilities Build and maintain the ASIC master schedule—including IP development, verification, physical implementation, package co‐design, MPW/test‐chip shuttles, qualification and production ramps. Drive weekly cross‐functional reviews and executive read‐outs. Directly manage and mentor the Analog and Digital ASIC Leads (and … via them, ~25 + engineers). Set goals, hire strategically, grow technical leaders and foster a culture of first‐pass silicon success. Provide architectural guidance and critical design‐review sign‐off for blocks running from > 20 GHz analog bandwidth to > 100 MHz digital core clocks . Resolve spec splits, timing closures, power budgets and mixed‐signal interactions. Act as … wafer starts, corner‐split strategies and yield‐learning plans. Own silicon CAPEX/OPEX budgets, mask and backend costs, and risk registers. Drive make/buy decisions for IP, EDA, test hardware and probe cards. Skills & Experience 15 + years in semiconductor development, with 3 + complex ASICs driven from concept through ramp‐to‐production at ≤ 22 nm . Demonstrated More ❯

people leadership and disciplined program management—all exercised across multiple concurrent tape‐outs. Responsibilities Build and maintain the ASIC master schedule—including IP development, verification, physical implementation, package co‐design, MPW/test‐chip shuttles, qualification and production ramps. Drive weekly cross‐functional reviews and executive read‐outs. Directly manage and mentor the Analog and Digital ASIC Leads (and … via them, ~25 + engineers). Set goals, hire strategically, grow technical leaders and foster a culture of first‐pass silicon success. Provide architectural guidance and critical design‐review sign‐off for blocks running from > 20 GHz analog bandwidth to > 100 MHz digital core clocks . Resolve spec splits, timing closures, power budgets and mixed‐signal interactions. Act as … wafer starts, corner‐split strategies and yield‐learning plans. Own silicon CAPEX/OPEX budgets, mask and backend costs, and risk registers. Drive make/buy decisions for IP, EDA, test hardware and probe cards. Skills & Experience 15 + years in semiconductor development, with 3 + complex ASICs driven from concept through ramp‐to‐production at ≤ 22 nm . Demonstrated More ❯