Reading, Berkshire, South East, United Kingdom Hybrid / WFH Options
Fortis Recruitment Solutions
to flight qualification. Key Skills & Experience Essential: Degree in Electronic/Electrical/Computer Engineering (or equivalent) Strong experience in digital design with VHDL and/or Verilog/SystemVerilog Proven track record performing synthesis, timing closure, and static timing analysis Experience with FPGA tool flows (e.g. Xilinx Vivado, Intel/Altera tools, or similar) Familiarity with simulation/verification More ❯
Southampton, Hampshire, South East, United Kingdom Hybrid / WFH Options
Fortis Recruitment Solutions
signal processing applications Contribute to architecture decisions, documentation, and technical reviews Collaborate across disciplines (design, verification, algorithms, implementation, system integration) Key Skills & Experience Essential: Expert knowledge of RTL (Verilog, SystemVerilog) for FPGA/ASIC products Strong track record delivering FPGA/ASIC digital designs Experience with synthesis, static timing analysis, power optimisation, and high-throughput design Proficiency with industry-standard More ❯
portsmouth, hampshire, south east england, united kingdom Hybrid / WFH Options
Fortis Recruitment Solutions
signal processing applications Contribute to architecture decisions, documentation, and technical reviews Collaborate across disciplines (design, verification, algorithms, implementation, system integration) Key Skills & Experience Essential: Expert knowledge of RTL (Verilog, SystemVerilog) for FPGA/ASIC products Strong track record delivering FPGA/ASIC digital designs Experience with synthesis, static timing analysis, power optimisation, and high-throughput design Proficiency with industry-standard More ❯
successful in this role you’ll need: A BSc/MSc/PhD in EEE/Maths/Physics Fluency in at least one of VHDL/Verilog/Systemverilog Ideally a Linux/Unix background It would be great if you also had: Knowledge of RISC-V/Arm/x86 Experience in ML or AI An understanding at More ❯
bachelor s degree in electronic engineering or a related field. At least 3+ years of commercial FPGA and general hardware design experience. Proficient in FPGA design using VHDL/SystemVerilog with AMD (Xilinx), Lattice, or Intel (Altera) products. Familiar with high-speed interfaces and advanced simulation methods. Strong communication skills for effective collaboration with team members and clients.What we offer More ❯
Langley, Slough, Berkshire, England, United Kingdom
Active Silicon
bachelor’s degree in electronic engineering or a related field. At least 3+ years of commercial FPGA and general hardware design experience. Proficient in FPGA design using VHDL/SystemVerilog with AMD (Xilinx), Lattice, or Intel (Altera) products. Familiar with high-speed interfaces and advanced simulation methods. Strong communication skills for effective collaboration with team members and clients. What we More ❯
Our client is seeking Firmware Engineers for contracts based in Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM More ❯
and space-qualified ASICs. As an FPGA Engineer, you will: Translate complex signal processing algorithms into efficient RTL architectures Design and verify FPGA and ASIC IP using Verilog/SystemVerilog Validate and integrate designs on the latest FPGA development platforms Collaborate across architecture, verification, and physical implementation teams Contribute to UVM test environments and technical documentation Key skills required for … the FPGA Engineer: Strong RTL experience (Verilog/SystemVerilog) targeting FPGAs or ASICs Skilled in timing closure, synthesis, and power/resource optimisation Experience working on high-throughput digital signal processing blocks Familiarity with communications algorithms (e.g. FEC, beamforming) is a bonus Knowledge of UVM, scripting (Python), or AMBA protocols is desirable If you’re interested in the position of More ❯