26 to 37 of 37 PCIe Jobs in the UK

Zephyr RTOS • Strong C and C++, plus Python and bash • Software flows for complex SoCs, co-simulation and hardware debug • Experience with 100GbE and PCIe • Proficient with Git and CI/CD • Familiarity with AMD Vivado and Vitis ...

architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance … using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration ...

integration, timing closure, place-and-route (P&R), constraints and optimisation . The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance … using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration ...

functional validation of a new SoC designed with high-end ARM processors . Execute functional bring-up of SoC interfaces such as LPDDR, Ethernet, PCIe, HBM, CPUs, Low-Speed IOs (UART, I2C, I3C, SPI), and Coherent Mesh. Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation … Verification, Electrical Testing & Characterization, and Production Firmware teams . Essential Skills Strong proficiency in Embedded C . Experience with high-speed protocols such as PCIe Gen6, die-to-die links, LPDDR5, and HBM3. Hands-on expertise with ARM high-end CPUs and ARM cache-coherent interconnect protocols . Proven validation ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as: LPDDR Ethernet PCIe HBM CPUs Low-Speed IOs (UART, I2C, I3C, SPI) Coherent Mesh Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation platforms … Verification teams Electrical Testing & Characterization teams Production Firmware teams Essential Skills Strong proficiency in Embedded C . Experience with high-speed protocols such as: PCIe Gen6 Die-to-die links LPDDR5 HBM3 Hands-on expertise with ARM high-end CPUs and ARM cache-coherent interconnect protocols . Proven validation experience ...

implement UVM/SystemVerilog verification environments Deliver constrained-random verification and achieve coverage sign-off Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5) Integrate and use Verification IP (VIP) Develop and maintain Python-based regression and CI workflows Collaborate with design, architecture, and SoC teams Essential … Skills & Experience Strong experience as a Verification Engineer/Design Verification Engineer Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience in ASIC, SoC, or IP verification environments Desirable Experience with ...

RTOS . Youll contribute to board bring-up, hardware/software co-debug, system verification, driver-level development , and support high-speed interfaces including PCIe and 100GbE . Collaboration with global engineering teams is central to this role. Key Skills Required Embedded software development in C/C++ , plus scripting … Strong experience with bare-metal , Yocto Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe , Ethernet , 100GbE , SerDes Proficient with Git , CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC , Vivado , Vitis Whats on Offer Long-term programme with ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as LPDDR, Ethernet, PCIe, HBM, CPUs, Low-Speed IOs (UART, I2C, I3C, SPI), and Coherent Mesh. Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation … Architects, RTL Verification, Electrical Testing & Characterization, and Production Firmware teams. Essential Skills Strong proficiency in Embedded C. Experience with high-speed protocols such as PCIe Gen6, die-to-die links, LPDDR5, and HBM3. Hands-on expertise with ARM high-end CPUs and ARM cache-coherent interconnect protocols. Proven validation experience ...

support bring-up and validation of SoCs based on high-performance ARM CPUs. Key Focus: Functional validation and bring-up of complex SoCs Interfaces: PCIe, LPDDR, HBM, Ethernet, low-speed IO (UART, I2C, SPI, I3C) Bare-metal Embedded C test development Debug on HAPS/Zebu emulation, followed by silicon … Cross-team collaboration (Architecture, RTL, Test, Firmware) Required Skills: Strong Embedded C ARM high-end CPUs & cache-coherent interconnects High-speed protocols (PCIe Gen6, LPDDR5, HBM3, die-to-die) Pre- and post-silicon validation experience Nice to Have: Python scripting Silicon bring-up High-speed interface driver development ...

contribute to innovative projects that push the boundaries of technology. The position focuses on high-speed digital design, with a particular emphasis on DDR, PCIe, and Ethernet technologies. The successful candidate will be responsible for designing, developing, and testing hardware components, ensuring they meet the highest standards of performance … passionate about advancing technological frontiers. Key Responsibilities for the Hardware Design Engineer: - Design and develop high-speed digital hardware components. - Implement and optimise DDR, PCIe, and Ethernet interfaces. - Conduct thorough testing and validation of hardware designs. - Collaborate with cross-functional teams to ensure seamless integration. - Troubleshoot and resolve design issues ...

contribute to innovative projects that push the boundaries of technology. The position focuses on high-speed digital design, with a particular emphasis on DDR, PCIe, and Ethernet technologies. The successful candidate will be responsible for designing, developing, and testing hardware components, ensuring they meet the highest standards of performance … passionate about advancing technological frontiers. Key Responsibilities for the Hardware Design Engineer: - Design and develop high-speed digital hardware components. - Implement and optimise DDR, PCIe, and Ethernet interfaces. - Conduct thorough testing and validation of hardware designs. - Collaborate with cross-functional teams to ensure seamless integration. - Troubleshoot and resolve design issues ...

execute UVM testbenches for unit-level and sub-system verification Perform coverage analysis and drive coverage closure to ensure verification completeness Work with PCIe, AMBA CHI, and AXI protocols for system verification Collaborate with design and verification teams to ensure timely delivery of high-quality designs Required Skills & Experience: Strong … experience with PCIe protocol verification Expertise in UVM methodology for both unit-level and sub-system level verification Hands-on experience with AMBA CHI & AXI interfaces Proven experience in coverage analysis and closure Strong problem-solving and debugging skills in a collaborative team environment Working Pattern: 3 days per week ...