176 to 200 of 304 Tcl Jobs in the UK

and desire to develop technical skills in areas such as database technologies and system performance. Ability to read and understand code in one or more of the following: C++, TCL, UNIX Scripting Ability to troubleshoot and approach problem solving in a logical manner Able to use own initiative, good attention to detail Technical Operations Analysts need to be dynamic, resilient More ❯

Knowledge of high-speed digital electronics. Knowledge of developing designs for AMD, Microsemi and/or Intel FPGAs. Knowledge of firmware simulation and verification tools. Knowledge of scripting, using TCL and/or Python. Knowledge of concepts such as Isolated Design Flow, encryption, and secure boot. Understanding of the engineering product development lifecycle. Ability to listen, understand and communicate effectively More ❯

and improving skills and knowledge Excellent problem-solving skills for debugging issues seen and finding root causes Ability to program/script (required to solve design issues, typically in Tcl and Python) Experience in 7nm or smaller technologies A good breadth of experience with physical design flows including: Floorplanning/Budgeting, Synthesis, Place and Route, Clock CTS, Timing Analysis, Logical More ❯

and improving skills and knowledge Excellent problem-solving skills for debugging issues seen and finding root causes Ability to program/script (required to solve design issues, typically in Tcl and Python) Experience in 7nm or smaller technologies A good breadth of experience with physical design flows including: Floorplanning/Budgeting, Synthesis, Place and Route, Clock CTS, Timing Analysis, Logical More ❯

and improving skills and knowledge Excellent problem-solving skills for debugging issues seen and finding root causes Ability to program/script (required to solve design issues, typically in Tcl and Python) Experience in 7nm or smaller technologies A good breadth of experience with physical design flows including: Floorplanning/Budgeting, Synthesis, Place and Route, Clock CTS, Timing Analysis, Logical More ❯

development Good knowledge of the appropriate IC design tools and process design kits for silicon chip design Cadence Virtuoso know-how Scripting experience in Linux/unix, python, Skill, TCL or other A competitive salary is on offer along with a strong range a benefits and total package. Get in touch for details! Contact caroline.pye@ic-resources.com More ❯

development Good knowledge of the appropriate IC design tools and process design kits for silicon chip design Cadence Virtuoso know-how Scripting experience in Linux/unix, python, Skill, TCL or other A competitive salary is on offer along with a strong range a benefits and total package. Get in touch for details! Contact caroline.pye@ic-resources.com More ❯

development Good knowledge of the appropriate IC design tools and process design kits for silicon chip design Cadence Virtuoso know-how Scripting experience in Linux/unix, python, Skill, TCL or other A competitive salary is on offer along with a strong range a benefits and total package. Get in touch for details! Contact caroline.pye@ic-resources.com More ❯

development Good knowledge of the appropriate IC design tools and process design kits for silicon chip design Cadence Virtuoso know-how Scripting experience in Linux/unix, python, Skill, TCL or other A competitive salary is on offer along with a strong range a benefits and total package. Get in touch for details! Contact caroline.pye@ic-resources.com More ❯

PnR, CTS, Static Timing Analysis) Debug and resolve complicated PPA, Low Power implementation and TAT issues. Exceptional troubleshooting and analytical skills Excellent command in scripting languages such as Perl, Tcl and shell scripting essentials Proven track record and experience working in a fast-paced environment We’re doing work that matters. Help us solve what others can’t. We’re More ❯

or Master's degree in Electronics or Electrical Engineering Good understanding of RTL to GDS implementation flow Experience working at 28nm, 16nm, 14nm, or 7nm process nodes Experience with TCL, Shell, Python, etc. Experience in tapeout procedures Expertise in timing constraints and STA Experience with DFT methodologies For more information on this role or others, please contact Jordan Browne. #J More ❯

to co‐design interposer, substrate and PCB break‐outs; model bond‐wire/micro‐bump parasitics in the extraction flow. Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work. Skills & Experience 7 + years of custom analog/RF IC layout in production CMOS technologies, with multiple … close sub‐pF capacitance budgets and Experience with flip‐chip, micro‐bump, 2.5D/3D IC or chiplet integration and the associated inductance/crosstalk challenges. Proficient in Skill, Tcl or Python to automate repetitive layout and sign‐off tasks. Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‐integrity and manufacturing teams in a fast‐moving More ❯

to co‐design interposer, substrate and PCB break‐outs; model bond‐wire/micro‐bump parasitics in the extraction flow. Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work. Skills & Experience 7 + years of custom analog/RF IC layout in production CMOS technologies, with multiple … geometry selection and EM‐aware verification. Experience with flip‐chip, micro‐bump, 2.5D/3D IC or chiplet integration and the associated inductance/crosstalk challenges. Proficient in Skill, Tcl or Python to automate repetitive layout and sign‐off tasks. Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‐integrity and manufacturing teams in a fast‐moving More ❯

to co‐design interposer, substrate and PCB break‐outs; model bond‐wire/micro‐bump parasitics in the extraction flow. Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work. Skills & Experience 7 + years of custom analog/RF IC layout in production CMOS technologies, with multiple … geometry selection and EM‐aware verification. Experience with flip‐chip, micro‐bump, 2.5D/3D IC or chiplet integration and the associated inductance/crosstalk challenges. Proficient in Skill, Tcl or Python to automate repetitive layout and sign‐off tasks. Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‐integrity and manufacturing teams in a fast‐moving More ❯

to co‐design interposer, substrate and PCB break‐outs; model bond‐wire/micro‐bump parasitics in the extraction flow. Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work. Skills & Experience 7 + years of custom analog/RF IC layout in production CMOS technologies, with multiple … geometry selection and EM‐aware verification. Experience with flip‐chip, micro‐bump, 2.5D/3D IC or chiplet integration and the associated inductance/crosstalk challenges. Proficient in Skill, Tcl or Python to automate repetitive layout and sign‐off tasks. Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‐integrity and manufacturing teams in a fast‐moving More ❯

to co‐design interposer, substrate and PCB break‐outs; model bond‐wire/micro‐bump parasitics in the extraction flow. Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work. Skills & Experience 7 + years of custom analog/RF IC layout in production CMOS technologies, with multiple … geometry selection and EM‐aware verification. Experience with flip‐chip, micro‐bump, 2.5D/3D IC or chiplet integration and the associated inductance/crosstalk challenges. Proficient in Skill, Tcl or Python to automate repetitive layout and sign‐off tasks. Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‐integrity and manufacturing teams in a fast‐moving More ❯

to co‐design interposer, substrate and PCB break‐outs; model bond‐wire/micro‐bump parasitics in the extraction flow. Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work. Skills & Experience 7 + years of custom analog/RF IC layout in production CMOS technologies, with multiple … geometry selection and EM‐aware verification. Experience with flip‐chip, micro‐bump, 2.5D/3D IC or chiplet integration and the associated inductance/crosstalk challenges. Proficient in Skill, Tcl or Python to automate repetitive layout and sign‐off tasks. Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‐integrity and manufacturing teams in a fast‐moving More ❯

to co‐design interposer, substrate and PCB break‐outs; model bond‐wire/micro‐bump parasitics in the extraction flow. Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work. Skills & Experience 7+years of custom analog/RF IC layout in production CMOS technologies, with multiple tape‐outs … close sub‐pF capacitance budgets and Experience with flip‐chip, micro‐bump, 2.5D/3D IC or chiplet integration and the associated inductance/crosstalk challenges. Proficient in Skill, Tcl or Python to automate repetitive layout and sign‐off tasks. Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‐integrity and manufacturing teams in a fast‐moving More ❯

As Lead Artist you are a role model and set standards in attitude, team spirit and content production by being an example. Skills Required: Expert Knowledge in Python/TCL/MEL Strong CG Generalist background Proven Maya and Nuke Experience Experience Required: CG Generalist background Experience Preferred: Working knowledge in game engine driven pipelines C++ Previous hands-on pipeline More ❯

As Lead Artist you are a role model and set standards in attitude, team spirit and content production by being an example. Skills Required : - Expert Knowledge in Python/TCL/MEL - Strong CG Generalist background - Proven Maya and Nuke Experience Experience Required : - CG Generalist background Experience Preferred : - Working knowledge in game engine driven pipelines - C++ - Previous hands-on pipeline More ❯

SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Berkshire. Visa sponsorship can be given for the right profile. This is a hybrid remote position More ❯

SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Berkshire. Visa sponsorship can be given for the right profile. This is a hybrid remote position More ❯

SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Berkshire. Visa sponsorship can be given for the right profile. This is a hybrid remote position More ❯

SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Berkshire. Visa sponsorship can be given for the right profile. This is a hybrid remote position More ❯

Power Gating, Multi-Voltage domains, and UPF/CPF Strong background in logic synthesis, static timing analysis, floorplanning, power grid planning, and physical verification Advanced knowledge of Python/TCL or Perl for scripting Note: 5V Tech is acting as an Employment Agency for this vacancy. We offer a reward scheme if you recommend someone for this position, up to More ❯