101 to 125 of 281 UVM Jobs in the UK

testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models, reusable testbenches, and randomized testing (SystemVerilog, UVM, or cocotb) Proficient in Python and C++ in a Linux environment Comfortable with CI/CD workflows (Jenkins, GitLab CI, Bamboo, etc.) Understanding of networking protocols such as TCP/ More ❯

testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models, reusable testbenches, and randomized testing (SystemVerilog, UVM, or cocotb) Proficient in Python and C++ in a Linux environment Comfortable with CI/CD workflows (Jenkins, GitLab CI, Bamboo, etc.) Understanding of networking protocols such as TCP/ More ❯

across block-level and system-level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already More ❯

timely updates on verification status. Qualifications • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. • Strong expertise in verification methodologies, such as UVM, and experience with PCIe, ethernet, and other relevant protocols. • Excellent leadership and communication skills with a track record of successfully leading verification teams. • Ability to thrive in a dynamic, fast More ❯

Work closely with the exec team to translate product requirements into hardware team deliverables. Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches. Lead engineering methodology, processes and design techniques. Nurture professional growth of team members through regular mentoring, coaching, and feedback Skills, Knowledge & Expertise: Track record of building and leading … for ASIC and FPGA. Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis. Understanding of UVM verification techniques or practical experience using UVM for IP verification. This is a Hybrid working role and you must be able to work onsite 2-3 days per week. For More ❯

design, on-chip communication and interconnects, high-speed interfaces, or chiplets. Expertise in Verilog/System Verilog for coding and verification. Proficiency in RTL design techniques. Experience in using UVM for functional verification of ASIC designs. Experience with FPGA OR emulation will be desirable. On offer is the opportunity to work for an organisation with an excellent environment, working culture More ❯

the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off Create verification plans, develop and maintain UVM testbench components Participate in all stages of design specification definition providing feedback from the verification perspective Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans. Be responsible … approach and details of a testbench Be able to do root-cause analysis of complex issues and resolve them in a timely manner Have excellent knowledge of SystemVerilog and UVM Be able to develop new verification flows For more information and a confidential discussion on this superb opportunity contact Rachel Mason at IC Resources. More ❯

design. A strong computer architecture background, preferably in graphics, and a strong foundation in verification methodology will be used to close testing coverage with high confidence. Description Use SystemVerilog, UVM and C++ with industry leading simulation tools and methodologies to verify complex GPU designs. Develop verification plans in coordination with design leads and architects. Create and maintain verification test bench More ❯

packages and driving them to success. Required Skills and Experience: Meticulous attention to detail, ensuring high-quality verification that minimizes bug escapes. Shown experience in block-level verification using UVM or similar methodologies. Strong knowledge of coverage driven verification for complex designs. Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches. Skilled in planning verification tasks and More ❯

encouraged to mentor junior members Required Skills and Experience : Tried understanding of digital hardware design and Verilog/Systemverilog HDL Experienced in one or more of various verification methodologies - UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯