51 to 75 of 100 UVM Jobs in the UK

engineers and system architects to define architectures, convert them to RTL, and ensure power and performance targets are met within hardware platforms. Experience with UVM/OSVVM would be useful in this role. #J-18808-Ljbffr ...

Electrical Engineering, Computer Engineering, or similar field At least ten years' of experience in analog/mixed-signal verification Proficiency in Virtuoso, SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium) A solid understanding of mixed-signal designs Experience with scripting languages (Python, Perl, Tcl) for automation Excellent language skills ...

experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate closely with ...

Formal Proof Tools. Familiarity with Formal Verification, Assertions, and Silicon bring-up. Keywords: CPU Verification/Design Verification/DV/SystemVerilog/UVM/Cache Coherence/Branch Prediction/Formal Verification/RIS/SOC/Assembly/Cambridge/Silicon Bring-up By applying to this role ...

module level and top level. Synthesis and timing analysis. Power and performance analysis. Integration of FPGAs into a target hardware platform. Experience of any UVM/OSVVM would be useful. #J-18808-Ljbffr ...

functional environment."Nice To Have" Skills and Experience :Experience with GPU, CPU or other complex processor architectures. Familiarity with verification methodologies including System Verilog, UVM or formal verification. Experience with industry-standard EDA tools (e.g. Cadence or Synopsys).Knowledge of requirements management tools such as Jama, DRM or similar. Exposure ...

Firmware/FPGA Engineer Permanent | United Kingdom | Predominantly Remote (typically one day per month on site) Akkodis is seeking an experienced Firmware/FPGA Engineer to join our growing Defence practice, supporting the delivery of ...

improved. What They're Looking For Experience managing or leading digital verification engineers Strong background in the verification of complex ICs Strong SystemVerilog and UVM experience, with knowledge of assertions and coverage-driven verification Experience developing verification strategies and using metrics such as code and functional coverage Ability to support ...

improved. What They're Looking For Experience managing or leading digital verification engineers Strong background in the verification of complex ICs Strong SystemVerilog and UVM experience, with knowledge of assertions and coverage-driven verification Experience developing verification strategies and using metrics such as code and functional coverage Ability to support ...

testing, and drive verification closure across RTL designs. You will collaborate with design and verification teams on tape-out-ready blocks, apply SystemVerilog/UVM, and leverage formal verification to expose corner cases, contributing to scalable, high-performance processors. #J-18808-Ljbffr ...

silicon team. This permanent, hybrid role offers involvement in OpenTitan Root of Trust and Ibex CPU verification. You will develop and debug SystemVerilog/UVM testbenches, create verification plans, and collaborate with design engineers to deliver high-quality silicon, while contributing to open-source projects and robust verification environments. #J ...

compute teams in Cambridge and Bristol. You will verify complex ASIC/processor designs, develop verification plans, and drive coverage to closure using SystemVerilog, UVM, SVA, and Python. Join a team at the forefront of AI compute and processor technology with flexible working and a strong compensation package ...

Imagination Technologies Limited is seeking a Principal GPU HW Verification Engineer in Bristol, UK, to oversee verification of GPU components. You will develop UVM testbenches, lead verification activities, and ensure project closure through metrics tracking. The ideal candidate will demonstrate strong expertise in verification methodologies, SystemVerilog, and communication skills ...

An opportunity has arisen within Leonardo Edinburgh for a Lead Firmware Engineer to work on the Global Combat Air System Programme (GCAP). Announced by the Prime Minister in December 2022, GCAP will deliver Tempest ...

Job Description: Your impact An exciting opportunity has arisen within Leonardo for a Lead Firmware/FPGA Specialist to work within the Surveillance Sector, developing firmware, working on FPGAs, that underpins both our current proven ...

experienced verification engineer to join its Systems Media IP team in Manchester. You will own and drive verification for a DPU subsystem, architect reusable UVM environments and contribute to verification strategy across multiple units and teams. The role focuses on planning, integration, and sign-off with emphasis on regression efficiency ...

## Firmware/FPGA Engineers - all levelsApplylocations: GB - Edinburgh: GB - Newcastletime type: Full timeposted on: Posted Todayjob requisition id: R0030762**Job Description:**Salary: Engineer: £37,400 to £53,550/Senior: £45, 200 to £61 ...

hackajob is partnering directly with Leonardo to hire for this role. Job Description: Salary: Engineer: £37,400 to £53,550/Senior: £45, 200 to £61,950/Principal: £53,300 to £71,400/ ...

close collaboration with Analog and Digital Design engineers. Description Definition and design of Self‐checking verification environments for multi‐layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks to ensure bug‐free tape‐outs. … support them are part of the AMS DV team’s DNA. Minimum Qualifications Knowledge of System Verilog test‐bench language and UVM (Universal Verification Methodology) Hands‐on experience with constrained random verification environments Basic design background in support of verification results analysis Knowledge of Object Oriented Programming (OOP) Proficiency ...

customers during presales and product development Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches Lead AccelerComm's engineering methodology, processes, and design techniques, integrating AI where possible. Nurture professional growth of team members through regular mentoring, coaching … including agile and waterfall, requirements capture and traceability. Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) Understanding of UVM verification techniques or practical experience using UVM for IP verification Experience with high speed interfaces on and off chip such as AMBA ...

Drive continuous improvement of verification processes through scripting, automation, and emerging AI technologies. PREFERRED EXPERIENCE: Proficient in IP-level ASIC verification. Strong experience with UVM testbenches and SystemVerilog. Proficient in debugging RTL and firmware using industry-standard simulation tools. Experience with Verilog, SystemVerilog, C, and C++. Experience developing UVM-based ...

synthesis Desirable: Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) Familiarity with the AMBA bus protocols Understanding of UVM verification techniques or practical experience using UVM for IP verification Experience using C++/SystemC for design modelling and integration Experience with high speed interfaces ...

synthesis Desirable: Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) Familiarity with the AMBA bus protocols Understanding of UVM verification techniques or practical experience using UVM for IP verification Experience using C++/SystemC for design modelling and integration Experience with high speed interfaces ...

opportunities both for engineers looking to broaden their skills across the full lifecycle and for those who want to specialise in areas such as UVM-based verification. As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance … Master's degree in Electronic Engineering (or related field)Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metricsSystemVerilog UVM testbenchesFormal proof verificationUnderstanding of C test cases and C codeScripting languages (e.g. Python, Perl, TCL)Desirable skillsExperience with formal verification tools (JasperGold, VC Formal)Familiarity ...

edge verification methodologiesContribute to and Influence the decisions on methodologies/strategies to be adopted for design verification. Develop testbench architectures and develop using UVM or Formal based verification approaches. Define verification-plans, functional coverage, tests and verification methodology for block/chip-level verification. Work with the design team …/Processor subsystems/Formal verificationExpert in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration. Excellent debugging and analytical skills. Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.10-15 years ...