London, England, United Kingdom Hybrid / WFH Options
microTECH Global LTD
closely with architects and RTL designers in an iterative development cycle Design Requirements 0–2 years of experience in RTL design using SystemVerilog or VHDL Solid foundation in digital logic design and computer architecture Exposure to or strong interest in GPU, AI accelerators, or vector processors Familiarity with RISC-V More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
and suppliers • Ensure designs are developed according to relevant standards • Manage engineers • Conduct peer reviews Competences and Skills Essential • Full lifecycle of electronics design • VHDL, Verilog, or SystemVerilog • Simulators, synthesis and place & route tools and hardware debug • Verification methodologies • Scripting languages (e.g. Python) • Revision Control Systems (e.g. Git or Subversion More ❯
to control subsystems + Create high-speed interfaces from FPGA to peripherals Skills and Experience Required: + Experience implementing DSP algorithms on FPGA using VHDL/Verilog + Understanding of digital & RF hardware + Experience interfacing FPGA with peripherals + Familiarity with the product life cycle Bonus: + Embedded C More ❯
Employment Type: Permanent
Salary: £50000 - £65000/annum Performance related bonus
Portsmouth, England, United Kingdom Hybrid / WFH Options
Enterprise Recruitment Ltd
years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Jira, Git VHDL High speed transceivers Memory controllers PCB Layout Location : WFH within reach of Portsmouth Seniority level Seniority level Mid-Senior level Employment type Employment type Full More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
IEC 62443, ISO 26262 Required Experience Experience of developing RTL design for digital electronics systems for Xilinx device architectures (or AMD/Lattice) using VHDL Experience in FPGA-SoC-implementation of algorithms developed in MATLAB/Simulink (algorithm development out of scope) Strong verification expertise in OSVVM/UVVM (or More ❯
