51 to 74 of 74 SystemVerilog Jobs in the UK excluding London

verification team Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems. Strong experience in UVM-based verification in SystemVerilog, with a deep understanding of the framework. Experience of verification coverage closure in an ASIC or FPGA project. Strong problem-solving skills. Experience of Synopsys functional ...

verification approaches (e.g. UVM/OSVVM/ABV). Bonus points for: experience with Xilinx/Intel (Altera)/Microchip devices; ModelSim/QuestaSim; SystemVerilog/Verilog; Layer-2/3 networking, USB 3.2 or NVMe; Red Hat Linux; interest in cryptographic systems. Excellent problem-solving, communication, and time-management … Engineer: Design and develop FPGA modules and subsystems across a range of devices and SoC platforms. Create clean, maintainable RTL (VHDL/Verilog/SystemVerilog); build testbenches and validate via simulation and hardware. Integrate FPGA blocks into wider system architectures; collaborate with software, hardware and verification colleagues. Keep pace with ...

adjust designs to ensure timing closure - Bring value with experience in Python based verification frameworks, such as cocotb (highly advantageous) Requirements: - Strong knowledge of SystemVerilog - Experience with Python - Proven background in RTL verification - Ability to write and validate timing constraints - Understanding of low power design principles - Experience writing module specifications ...

closely related field Minimum of 4 years of relevant industry experience Special Requirements Universal Verification Methodology TCL and Bash scripting Formal verification techniques SystemVerilog Salary and benefits £50,000 – £60,000 per annum base salary, dependent on experience and skill set Bonus and/or equity participation available Industry-standard ...

Waveform viewers, and Formal Proof Tools. Familiarity with Formal Verification, Assertions, and Silicon bring-up. Keywords: CPU Verification/Design Verification/DV/SystemVerilog/UVM/Cache Coherence/Branch Prediction/Formal Verification/RIS/SOC/Assembly/Cambridge/Silicon Bring ...

Bristol Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

Senior FPGA Engineer 13412 This position is perfect for an FPGA Engineer focused on innovation. You will be ahead of industry trends, collaborating with leading semiconductor companies and top engineers on challenging projects. In this ...

edge sign-off methodologies. Key requirements: Mastery of industry-standard formal tools (e.g., JasperGold, VC Formal, or Questa Formal). Hands-on expertise writing SystemVerilog Assertions. PExperience in deep bug-hunting, coverage closure, and achieving formal sign-off on complex IPs. Knowledge of GPU architectures or sequential equivalence checking ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding ...

create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design and DV engineers … Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used by industry leading Companies. Experience of working on projects with teams located internationally. … z2bz0 years of digital ASIC design and verification experience Vast experience of: Translating design requirements into RTL Deriving functional requirements for verification Systemverilog UVM test benches Scripting languages & REST API’s (e.g. Perl/Python/TCL) Team player with good verbal and written communication skills Verification Engineer Desirable skills ...

Design Verification Engineer This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on ...

Design Verification Engineer This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on ...

exciting opportunity for a Senior Staff Verification Engineer to join a global R&D organisation. In this role, you will be responsible for developing SystemVerilog UVM testbench environments for IP-level verification, as well as designing and implementing new UVM verification components. You will ensure that verification environments meet … verification strategy and testbench architecture across the business. Key Requirements Minimum of 7 years’ experience in hardware verification, ideally at IP level, using SystemVerilog and UVM Advanced expertise in UVM, SystemVerilog, and SystemVerilog Assertions (SVAs) Experience developing verification platforms and frameworks Proven ownership of IP verification, including delivery against defined ...

Description: Role: Senior IP Design EngineerType: ContractLocation: Belfast, UK Hybrid Job details:Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills:SystemVerilog RTL design100Gb Ethernet, PCIe Gen5, AMBA/AXIDeep understanding of FPGA/Adaptive ...

Job Title: Microarchitect & RTL Design Engineer Location: England, United Kingdom (office location yet to be determined) About the Role: We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture ...

Design Verification Engineer - CPU DV/Microprocessor Verification/SystemVerilog/UVM We are partnered with a global semiconductor company with a major engineering presence in Cambridge. They are looking for a CPU Design Verification Engineer to work on high performance CPU and SoC products across a broad range ...

Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding xkybehq ...

Take the initiative in developing reusable RTL for implementing clever algorithms For this role, we are seeking an academically bright candidate, PhD-qualified in a numerate stem subject such as physics, maths, electronics, or electronics ...

Use your digital logic problem-solving skills to develop cutting-edge reusable designs For this role, we are seeking an academically bright graduate in a numerate stem subjects such as physics, maths, electronics or a ...

block- and system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements … 5+ years industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. JBRP1_UKTJ ...

block- and system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements … 5+ years industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...