51 to 72 of 72 SystemVerilog Jobs in the UK excluding London

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage Review open-source contributions and debug regressions Contribute to test and CI infrastructure Collaborate with partners … support successful tapeouts Requirements Essential 5+ years industry experience in design verification Strong SystemVerilog and UVM experience Full verification lifecycle experience through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience Security ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...

with quarterly visits to London. What You'll Do Own unit‐level and core‐level verification for complex digital IP Build scalable SystemVerilog/UVM environments Develop constrained‐random and directed tests to drive high coverage Debug failures across RTL, testbench, and micro‐architecture Automate regressions and flows using Python … with modern IP ecosystems: microprocessor cores, memory subsystems, AMBA interconnects, system debug logic What You Bring 3–4+ years of digital verification experience Strong SystemVerilog/UVM expertise Solid understanding of digital logic and verification methodologies Experience with ARM‐based components (M‐class cores, NIC, Coresight, AMBA protocols) Familiarity with ...

including data paths, block functionality, and interfaces Define and execute Formal Property Verification (FPV) strategies and test plans Develop assertion-based verification environments using SystemVerilog Assertions (SVA) Debug RTL issues and drive formal sign-off and coverage closure Collaborate closely with RTL design, architecture, and dynamic verification teams across global … Formal Verification within ASIC, SoC, or GPU-adjacent environments Strong hands-on experience with industry-standard formal verification tools Proven expertise writing and debugging SystemVerilog Assertions (SVA) Experience achieving formal coverage closure and sign-off Strong RTL debug and problem-solving skills Excellent communication skills and ability to work cross ...