51 to 75 of 83 SystemVerilog Jobs in the UK excluding London

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related discipline. Proven track record in ASIC verification , ideally with experience in complex SoC designs. Proficiency in SystemVerilog and UVM methodology . WiFi or wireless SoC experience is highly desirable. Strong leadership skills with the ability to mentor and influence. Excellent communication and collaboration skills. What you’ll More ❯

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related discipline. Proven track record in ASIC verification , ideally with experience in complex SoC designs. Proficiency in SystemVerilog and UVM methodology . WiFi or wireless SoC experience is highly desirable. Strong leadership skills with the ability to mentor and influence. Excellent communication and collaboration skills. What you’ll More ❯

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related discipline. Proven track record in ASIC verification , ideally with experience in complex SoC designs. Proficiency in SystemVerilog and UVM methodology . WiFi or wireless SoC experience is highly desirable. Strong leadership skills with the ability to mentor and influence. Excellent communication and collaboration skills. What you’ll More ❯

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related discipline. Proven track record in ASIC verification , ideally with experience in complex SoC designs. Proficiency in SystemVerilog and UVM methodology . WiFi or wireless SoC experience is highly desirable. Strong leadership skills with the ability to mentor and influence. Excellent communication and collaboration skills. What you’ll More ❯

. 8+ years of hands-on experience in microarchitecture and RTL design. Proven experience as a team or technical lead within ASIC/SoC projects. Proficiency in Verilog and SystemVerilog . Strong knowledge of EDA tools and flows . In-depth expertise with on-chip interconnects and NoCs . Experience designing cache/memory subsystems, interconnects, or NoCs is a More ❯

. 8+ years of hands-on experience in microarchitecture and RTL design. Proven experience as a team or technical lead within ASIC/SoC projects. Proficiency in Verilog and SystemVerilog . Strong knowledge of EDA tools and flows . In-depth expertise with on-chip interconnects and NoCs . Experience designing cache/memory subsystems, interconnects, or NoCs is a More ❯

About this Position: We are seeking an experienced Senior/Principal FPGA Engineer to join a dynamic team working on cutting-edge systems within the aerospace and defence industry. This role focuses on designing and developing FPGA solutions using VHDL More ❯

About this Position: We are seeking an experienced Senior/Principal FPGA Engineer to join a dynamic team working on cutting-edge systems within the aerospace and defence industry. This role focuses on designing and developing FPGA solutions using VHDL More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland. Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE) I am looking for a SOC Chip design Lead More ❯

RISC-V cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI. Key Responsibilities Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM Develop test and coverage plans for new and updated designs Triage and debug nightly regressions Review contributions to open-source projects Enhance test and CI infrastructure Collaborate on … academic/industry publications Stay current with verification best practices and introduce improvements Candidate Requirements Essential: 5+ years industry experience in design verification Strong SystemVerilog and UVM expertise Experience across the full verification cycle (planning to tape-out) Able to provide estimates and coordinate with project managers Comfortable in multidisciplinary, multi-organisation teams Familiar with Git and code review tools More ❯

to innovative hardware solutions. Responsibilities : Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans, failure debug, coverage, etc. Qualifications … MS in Electrical Engineering, Computer Engineering or Computer Science 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Deep experience with UVM-based testbenches Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IP More ❯

to innovative hardware solutions. Responsibilities : Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans, failure debug, coverage, etc. Qualifications … MS in Electrical Engineering, Computer Engineering or Computer Science 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Deep experience with UVM-based testbenches Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IP More ❯

with specifications. Key Responsibilities: Develop and execute formal verification plans for digital blocks and systems. Identify key properties and invariants for verification using formal methods. Write formal specifications using SystemVerilog Assertions (SVA), PSL, or other formal languages. Analyze formal verification results, including counterexamples and traces, and collaborate with design teams to resolve issues. Integrate formal methods into the overall verification … Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. Solid understanding of digital design principles, including RTL design (Verilog/SystemVerilog, VHDL). Experience with formal verification tools and methodologies. Strong knowledge of logic, Boolean algebra, and formal specification languages. Familiarity with common bus protocols and microarchitecture concepts. Non UK nationals More ❯

with specifications. Key Responsibilities: Develop and execute formal verification plans for digital blocks and systems. Identify key properties and invariants for verification using formal methods. Write formal specifications using SystemVerilog Assertions (SVA), PSL, or other formal languages. Analyze formal verification results, including counterexamples and traces, and collaborate with design teams to resolve issues. Integrate formal methods into the overall verification … Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. Solid understanding of digital design principles, including RTL design (Verilog/SystemVerilog, VHDL). Experience with formal verification tools and methodologies. Strong knowledge of logic, Boolean algebra, and formal specification languages. Familiarity with common bus protocols and microarchitecture concepts. Non UK nationals More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

ASIC Design Engineer – Cambridge/UK Remote A US-based start-up has recently expanded into the UK and is building a cutting-edge hardware team comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team More ❯