51 to 75 of 214 UVM Jobs in the UK excluding London

features utilizing CHERI technology. Responsibilities Collaborates with the design team to understand and define verification requirements for security features Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology Executes test plans and verifies the correctness of hardware security features Works closely with the cross-functional teams to ensure the implementation meets design specifications and security requirements Identifies … manner Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Strong understanding of hardware verification methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity with security features and protocols, such as CHERI, is a plus Excellent communication skills and the ability to work effectively in a collaborative More ❯

features utilizing CHERI technology. Responsibilities Collaborates with the design team to understand and define verification requirements for security features Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology Executes test plans and verifies the correctness of hardware security features Works closely with the cross-functional teams to ensure the implementation meets design specifications and security requirements Identifies … manner Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Strong understanding of hardware verification methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity with security features and protocols, such as CHERI, is a plus Excellent communication skills and the ability to work effectively in a collaborative More ❯

responsible for ensuring the exceptional quality of complex graphics IP designs. You will collaborate with multi-functional teams to tackle new challenges, requiring robust written and verbal abilities.Using SystemVerilog, UVM, C++, and scripting languages, you will develop test benches, generate tests, run and debug simulations to drive our complex graphics IPs to high-quality closure.As you progress, you'll take More ❯

to the development of WiFi products and will play a crucial role in the low-power verification and verification of system-on-chip (SoC) designs. Responsibilities Develops and implements UVM-based testbenches for ASIC verification Verifies low-power design features and optimizes power consumption Contributes to the verification of SoC designs Collaborates with cross-functional teams to ensure high-quality … and debugs complex hardware designs Qualifications Bachelor's or Master's degree in Electrical Engineering or related field Solid experience in ASIC verification and hardware design Proficiency in developing UVM-based testbenches Familiarity with C programming for testbenches Knowledge of low-power verification techniques Experience in the development of WiFi products is a plus Excellent communication and problem-solving skills … Can sponsor those already in the UK Day-to-Day Collaborating with the design team to understand the design intent Developing and maintaining UVM-based testbenches Running simulations and debugging issues Participating in design and code reviews Writing and maintaining verification test plans and documentation Communicating with cross-functional teams to ensure project alignment More ❯

and don't miss this opportunity to join Infineon's success story. As a Staff Verification Engineer, you will play a critical role in developing and maintaining System Verilog - UVM test benches, solving complex problems, and develop new SV UVM verification components. Your responsibilities will also include understanding and modifying Specman-e test benches, debugging failing test cases, and defining … the verification strategy and architecture of IP testbenches, ensuring test bench quality, and meeting sign-off targets. In your new role, you will: Be responsible for developing System Verilog - UVM testbench and solve potentially complex problems related to test bench development Be responsible and lead developing of new SV UVM verification components Be able to understand and modify Specman-e … A Bachelor's degree in Electrical/Electronic Engineering or equivalent degree At least 3 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM; Prior knowledge in Specman-e is desirable Advanced knowledge in UVM and SVAs, System Verilog Experience with Verification platform and framework development Proven experience of ownership of IP verification including More ❯

and don't miss this opportunity to join Infineon's success story. As a Principal Verification Engineer, you will play a critical role in developing and maintaining System Verilog - UVM test benches, solving complex problems, and leading the development of new SV UVM verification components. Your responsibilities will also include understanding and modifying Specman-e test benches, debugging failing test … the verification strategy and architecture of IP testbenches, ensuring test bench quality, and meeting sign-off targets. In your new role, you will: Be responsible for developing System Verilog - UVM testbench and solve potentially complex problems related to test bench development Be responsible and lead developing of new SV UVM verification components Able to understand and modify Specman-e test … A Bachelor's degree in Electrical/Electronic Engineering or equivalent degree At least 10 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM; Prior knowledge in Specman-e is desirable Advanced knowledge in UVM and SVAs, System Verilog Experience with Verification platform and framework development Proven experience of ownership of IP verification including More ❯

role, shaping the future of the verification team. What You'll Need: In-depth understanding of verification flows, test plans, and strategies. Expertise in constrained-random SystemVerilog testbenches using UVM or VMM. Experience in creating and examining functional coverage and writing SystemVerilog assertions. Skills in debugging RTL and gate-level simulation failures and firmware. Familiarity with bug tracking tools like More ❯

Engineer, Senior : Design Verification of custom V&M and IoT IP and SoCs, including: Design analysis for testability Test planning Test bench and infrastructure development using System Verilog and UVM IP level test development using System Verilog and UVM IP level test development using Formal Methods SoC level test development using System Verilog and embedded C code Work is in … a dynamic team environment. Skills and Experience we would love to see Experience of System Verilog, Verilog Experience of UVM Experience of C or other high-level languages SV-UVC development UVM testcase development Strong debug skills Knowledge of Standard interfaces, Bus protocols and Processor architectures Proven track-record of delivering quality verification on time Enthusiasm to learn in a … Qualifications Education: Masters - Computer Engineering, Masters - Computer Science, Masters - Electrical Engineering Work Experiences: 3 yrs+ in an appropriate Design Verification role, with hands-on experience of designing and coding UVM UVCs and test cases. Skills: System Verilog, UVM, Embedded C, Design Verification, Python WE INVENT THE TECH THE WORLD LOVES, SO IF YOU ARE INTERESTED IN LEARNING MORE What's More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯