101 to 125 of 185 Verification Engineer Jobs

a growing UK based company in their UK HQ! The specific Wi-Fi IC Group is looking to strengthen their team with a Junior Verification Engineer who has knowledge and understanding of SoC and IP level verification. This role is not limited to but would best suit someone … Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial experience. Knowledge of verification planning, assertion based and formal verification techniques, metric driven verification with UVM and C testbenches. Experience with low power verification and More ❯

talent, offering full technical freedom, rare foundry access, and long-term stability in a low-politics, high-impact environment. They're hiring a Senior Verification Engineer to help build their verification infrastructure. Responsibilities Implement verification infrastructure and test cases in collaboration with the design team and … partners. Debug failures, create and track issues to resolution. Develop and maintain automated regression test infrastructure and gatekeepers. Requirements Deep expertise in industry-standard verification methodologies, including proficiency with SystemVerilog and UVM. Experience with GPUs/CPUs is highly desirable. Demonstrated ability to collaborate effectively with design teams to More ❯

talent, offering full technical freedom, rare foundry access, and long-term stability in a low-politics, high-impact environment. They're hiring a Senior Verification Engineer to help build their verification infrastructure. Responsibilities Implement verification infrastructure and test cases in collaboration with the design team and … partners. Debug failures, create and track issues to resolution. Develop and maintain automated regression test infrastructure and gatekeepers. Requirements Deep expertise in industry-standard verification methodologies, including proficiency with SystemVerilog and UVM. Experience with GPUs/CPUs is highly desirable. Demonstrated ability to collaborate effectively with design teams to More ❯

Position: ASIC Verification Engineer Location: Oxfordshire, UK Full time/Perm: Office based & hybrid working arrangement with the option to work from home on Monday and Fridays. About the Client: My client is one of the leading providers of high-performance client, data centre and enterprise solid-state … architecture, firmware and validation. Essential qualifications and skills: - Bachelor or Master's degree in Electronic Engineering or related field - 12+ years of digital ASIC verification experience - Practical experience and understanding of: - Requirement capture, verification planning and coverage closure - System Verilog and UVM test benches - Creation of UVM test More ❯

Position: ASIC Verification Engineer Location: Oxfordshire, UK Full time/Perm: Office based & hybrid working arrangement with the option to work from home on Monday and Fridays. About the Client: My client is one of the leading providers of high-performance client, data centre and enterprise solid-state … architecture, firmware and validation. Essential qualifications and skills: - Bachelor or Master’s degree in Electronic Engineering or related field - 12+ years of digital ASIC verification experience - Practical experience and understanding of: - Requirement capture, verification planning and coverage closure - System Verilog and UVM test benches - Creation of UVM test More ❯

Analog & Mixed Signal Verification Engineer Salary: Very Attractive Rate Location: N/A Contract Senior Analog & Mixed Signal Verification EngineerResponsibilities will include: Perform verification simulations and generate design documentation for ASIC development projects Design suitable test benches in both Virtuoso Analog Design Environment or VHDL as … necessary Present results to the ASIC project team to feedback block performance Flag any performance issues early in the design cycle Generate verification reports and design documents for all key blocks Lead/participate in peer design reviews Generate ASIC operation manual The role may also include definition and More ❯

Position: GPU Formal Verification Engineer Contract: Permanent Salary: Negotiable + 20% variable The role: The role is for our fast-growing GPU Hardware team. Our mission is to create through constant innovation the best-in-class GPU IP, for a wide range of market segments and applications. By … market-leading chips and deliver significant impact to the future success of our wider team. You will: Be responsible for the delivery of formal verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off. Design and implement formal verification strategies to achieve our design quality goals. Root-cause design issues in collaboration with other engineers. Research new formal verification techniques and continuously drive the scope of what can be achieved with formal verification. Create verification plans, develop and maintain formal methodology and complex benches. Track and More ❯

developing IC that has high-impact applications across machine learning, aerospace and automotive. Flat structure with a highly diverse workload and excellent benefits. Senior Verification Engineer Responsibilities: Develop and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies … resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures is preferred. Proven ability to work effectively More ❯

Role: ASIC Verification Engineer Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Contract: Long-Term | Outside IR35 Rate: Competitive/Negotiable About the Company: This is a forward-thinking technology company developing ground-breaking silicon IP solutions that span compute, AI, graphics, memory, communications, and security. These IPs … role offers a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool More ❯

We are hiring for three exciting hardware verification roles in the UK with hybrid flexibility and strong growth potential. Join a fast-growing start-up working on next-gen silicon IP across AI, graphics, compute, and security. You will contribute to cutting-edge ASIC verification and play a … shaping high-performance chips. If you are looking for real impact and innovation, or know someone who might be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years’ experience, strong SystemVerilog …/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs Requirements: 5+ years’ experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent More ❯

We are hiring for three exciting hardware verification roles in the UK with hybrid flexibility and strong growth potential. Join a fast-growing start-up working on next-gen silicon IP across AI, graphics, compute, and security. You will contribute to cutting-edge ASIC verification and play a … shaping high-performance chips. If you are looking for real impact and innovation, or know someone who might be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years experience, strong SystemVerilog …/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs Requirements: 5+ years experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent More ❯

Social network you want to login/join with: Senior Design Verification Engineer, slough col-narrow-left Client: Platform Recruitment Location: slough, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 4 Posted: 31.05.2025 Expiry Date: 15.07.2025 col-wide Job Description: Join … has high-impact applications across machine learning, aerospace and automotive. Flat structure with a highly diverse workload and excellent benefits. Responsibilities: Develop and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies and architectures to ensure product quality and performance. … resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures is preferred. Proven ability to work effectively More ❯

Social network you want to login/join with: Senior Design Verification Engineer, brighton col-narrow-left Client: Platform Recruitment Location: brighton, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 4 Posted: 31.05.2025 Expiry Date: 15.07.2025 col-wide Job Description: Join … has high-impact applications across machine learning, aerospace and automotive. Flat structure with a highly diverse workload and excellent benefits. Responsibilities: Develop and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies and architectures to ensure product quality and performance. … resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures is preferred. Proven ability to work effectively More ❯

Social network you want to login/join with: Senior Design Verification Engineer, west london col-narrow-left Client: Platform Recruitment Location: west london, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 10 Posted: 06.06.2025 Expiry Date: 21.07.2025 col-wide Job … has high-impact applications across machine learning, aerospace and automotive. Flat structure with a highly diverse workload and excellent benefits. Responsibilities: Develop and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies and architectures to ensure product quality and performance. … resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures is preferred. Proven ability to work effectively More ❯

Social network you want to login/join with: Senior Design Verification Engineer, crawley, west sussex col-narrow-left Client: Platform Recruitment Location: crawley, west sussex, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 9 Posted: 06.06.2025 Expiry Date: 21.07.2025 col … has high-impact applications across machine learning, aerospace and automotive. Flat structure with a highly diverse workload and excellent benefits. Responsibilities: Develop and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies and architectures to ensure product quality and performance. … resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures is preferred. Proven ability to work effectively More ❯

Social network you want to login/join with: Senior Design Verification Engineer, south west london col-narrow-left Client: Platform Recruitment Location: south west london, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 4 Posted: 31.05.2025 Expiry Date: 15.07.2025 col … has high-impact applications across machine learning, aerospace and automotive. Flat structure with a highly diverse workload and excellent benefits. Responsibilities: Develop and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies and architectures to ensure product quality and performance. … resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures is preferred. Proven ability to work effectively More ❯

on site for 4/5 days per week and is a on secure site where SC clearance is needed. As a Validation and Verification Engineer you'll support product development for the system. Day to day you'll be supporting and producing the definition of the Test … Scenarios and success criteria to ensure the product meet its requirements. The role will also involve production of the appropriate verification plans to agree with the equipment DA the method of verification used. Skills, Qualification and Experience Degree or equivalent qualification in Systems engineering or similar Systems design … most recently receiving three accreditation gold standard awards with Investors in People! "Interesting work. Good work-life balance. Employees made to feel valued." Software Engineer, 5 Dec 2022. *Glassdoor review. "Promotes and believes in a good work/life balance interesting work on most programmes Encourages internal mobility. Offers More ❯

on site for 4/5 days per week and is a on secure site where SC clearance is needed. As a Validation and Verification Engineer you'll support product development for the system. Day to day you'll be supporting and producing the definition of the Test … Scenarios and success criteria to ensure the product meet its requirements. The role will also involve production of the appropriate verification plans to agree with the equipment DA the method of verification used. Skills, Qualification and Experience Degree or equivalent qualification in Systems engineering or similar Systems design … most recently receiving three accreditation gold standard awards with Investors in People! 'Interesting work. Good work-life balance. Employees made to feel valued.' Software Engineer, 5 Dec 2022. *Glassdoor review. 'Promotes and believes in a good work/life balance interesting work on most programmes Encourages internal mobility. Offers More ❯

Join our latest project! Currently we’re looking for a Verification Engineer to join our client in Scotland. This client is a market leader in the defence and aerospace industry. This project will be an initial 6 month deployment outside of IR35. This role can be worked predominantly … of the project. In order to suit the project requirements you should have some of the following: Expertise in VHDL/SystemsVerilog Writing detailed verification test plans Developing design verification test benches for FPGA modules/systems This is requirement is due to start mid June. If you More ❯

Social network you want to login/join with: Design Verification Engineer, Chelmsford Client: ALOIS Solutions Location: Job Category: Other - EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description: Verify CPU connectivity to IP blocks (using ASM boot , and C code, GNU … toolchain ) Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all the design blocks in the SoCs/Subsystems. Run regressions, debug test failures, and file bug reports as needed. Develop tests to meet functional and code coverage requirements … based on analysis of coverage gaps. Provide verification reports showing all tests passing on the RTL. Methodologies include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

Social network you want to login/join with: Design Verification Engineer, Newcastle-upon-Tyne, Tyne and Wear Client: ALOIS Solutions Location: Newcastle-upon-Tyne, Tyne and Wear, United Kingdom Job Category: Other EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description … to IP blocks (using ASM boot , C code, GNU toolchain ) Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all the design blocks in the SoCs/Subsystems. Run regressions, debug test failures, and file bug reports as needed. … Develop tests to meet functional and code coverage requirements based on analysis of coverage gaps. Provide verification reports demonstrating all tests passing on RTL. Utilize methodologies including design checks, verification with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J More ❯

Social network you want to login/join with: Design Verification Engineer, Warrington, Cheshire Client: ALOIS Solutions Location: Warrington, Cheshire Job Category: Other EU work permit required: Yes Job Views: 5 Posted: 09.06.2025 Expiry Date: 24.07.2025 Job Description: Verify CPU connectivity to IP blocks (using ASM boot , C … code, GNU toolchain ) Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all design blocks in the SoCs/Subsystems. Run regressions, debug test failures, and file bug reports as needed. Develop tests to meet functional and code coverage … requirements based on coverage gap analysis. Provide verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

Social network you want to login/join with: Design Verification Engineer, Watford, Hertfordshire Client: ALOIS Solutions Location: Watford, Hertfordshire, United Kingdom Job Category: Other EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description: Verify CPU connectivity to IP blocks (using ASM … boot , C code, GNU toolchain ) Write test plans, define test methodologies, develop test benches, write testcases, complete functional verification, and close coverage for all design blocks in the SoCs/Subsystems Run regressions, debug test failures, and file bug reports as needed Develop tests to meet functional and code … coverage requirements based on analysis of coverage gaps Provide verification reports demonstrating all tests pass on the RTL Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/System Verilog testbenches, C, System Verilog, UVM testcases #J-18808-Ljbffr More ❯

Social network you want to login/join with: Design Verification Engineer, Portsmouth, Hampshire Client: ALOIS Solutions Location: Portsmouth, Hampshire, United Kingdom Job Category: Other EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description: Verify CPU connectivity to IP blocks (using ASM … boot , and C code, GNU toolchain ) Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all the design blocks in the SoCs/Subsystems. Run regressions, debug test failures, and file bug reports as needed. Develop tests to meet … functional and code coverage requirements based on analysis of coverage gaps. Provide verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J More ❯

Social network you want to login/join with: Design Verification Engineer, Stoke-on-Trent Client: ALOIS Solutions Location: Stoke-on-Trent, United Kingdom Job Category: Other EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description: Verify CPU connectivity to IP blocks … using ASM boot , and C code, GNU toolchain ) Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all the design blocks in the SoCs/Subsystems Run regressions, debug test failures, and file bug reports as needed Develop tests … to meet functional and code coverage requirements based on analysis of coverage gaps Provide verification reports showing all tests passing on the RTL Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog-based testbenches, and C, SystemVerilog, UVM-based test cases More ❯