51 to 68 of 68 SystemVerilog Jobs in London

and milestones clearly and consistently Support synthesis and physical design teams during integration and bring-up phases Verification Responsibilities Develop and maintain UVM/SystemVerilog testbenches for functional verification Write both directed and random tests to verify design correctness and improve coverage Run regressions and assist with debugging RTL and … behavior Work closely with architects and RTL designers in an iterative development cycle Design Requirements 0–2 years of experience in RTL design using SystemVerilog or VHDL Solid foundation in digital logic design and computer architecture Exposure to or strong interest in GPU, AI accelerators, or vector processors Familiarity with … Engineering, or a related discipline Verification Requirements 0–2 years of hands-on experience with hardware verification (academic or internship projects count) Familiar with SystemVerilog and basic UVM concepts Interest or exposure to functional coverage, assertions, and constrained-random testing Understanding of GPU/AI workloads or RISC-V architecture More ❯

help architect and build a hardware platform for low-latency trading. The role involves varied responsibilities, including: Developing low-latency designs in Verilog/SystemVerilog Creating test harnesses to verify designs using self-checking test benches, BFMs, etc. Integrating firmware on target hardware with other system components and software The … of 3 years of industry experience in hardware development Hands-on digital design and FPGA architecture experience Proficiency in writing RTL in Verilog/SystemVerilog or VHDL Strong problem-solving and debugging skills BSc in Electronics/Engineering or related field, or equivalent experience Experience with self-checking testbenches, BFMs More ❯

Social network you want to login/join with: Founded by experienced quantitative trades, this is one of the largest firms by trading volume on Indian exchanges with a significant market share on several large global exchanges. They’re looking More ❯

Join to apply for the Design Verification Engineer role at G-Research Join to apply for the Design Verification Engineer role at G-Research Get AI-powered advice on this job and more exclusive features. Do you want to tackle More ❯

will ensure first‐silicon success and robust, production‐worthy silicon that scales to data‐centre volumes. Responsibilities Architect, implement and maintain comprehensive verification environments (SystemVerilog + UVM, assertion‐based and formal) for datapath, control, memory and high‐speed I/O blocks in our OTPU. Define verification plans that target … the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low More ❯

will ensure first‐silicon success and robust, production‐worthy silicon that scales to data‐centre volumes. Responsibilities Architect, implement and maintain comprehensive verification environments (SystemVerilog + UVM, assertion‐based and formal) for datapath, control, memory and high‐speed I/O blocks in our OTPU. Define verification plans that target … the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low More ❯

will ensure first‐silicon success and robust, production‐worthy silicon that scales to data‐centre volumes. Responsibilities Architect, implement and maintain comprehensive verification environments (SystemVerilog + UVM, assertion‐based and formal) for datapath, control, memory and high‐speed I/O blocks in our OTPU. Define verification plans that target … the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low More ❯

FPGA Engineer - London or Amsterdam - Leading High Frequency Trading Firm Summary This is a fantastic opportunity to work at a tech-focused market maker with groundbreaking success in high frequency trading. The company culture is competitive yet collaborative, leveraging advanced More ❯

Swedium Global Services is a growing System Engineering and Solution Company, offering services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy, and Outsourcing services to our clients More ❯

areas like memory, interconnect, and high-speed interface design. Key Responsibilities: + Develop and Integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) + Undertake Digital IC Design processes & Perform design synthesis, linting + Complete projects from conception to completion Skills Required: + Experience with frontend … RTL Design + Strong Experience with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. A competitive salary, bonus More ❯

technical decision-making Document technical specifications and development progress Contribute to bring-up, synthesis, and physical-aware design flows Verification Responsibilities: Develop UVM/SystemVerilog testbenches and functional verification plans Implement directed and constrained-random tests for robust coverage Execute regression testing, debug RTL, and track issues to resolution Verify … Measure and validate system performance and functional correctness Collaborate closely with RTL designers and architects Design Requirements: 5+ years of experience in RTL design (SystemVerilog or VHDL) Deep knowledge of digital design principles and computer architecture Experience with GPU, vector processors, or AI accelerator design Familiarity with RISC-V instruction … Electrical Engineering, Computer Engineering, or related field Verification Requirements: 5+ years of experience in hardware verification (complex SoCs preferred) Strong understanding of UVM and SystemVerilog methodologies Experience with advanced verification techniques (coverage, assertions, formal) Familiarity with RISC-V and GPU/AI architectures (preferred) Proficient with simulators and debug tools More ❯

Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

areas like memory, interconnect, and high-speed interface design. Key Responsibilities: + Develop and integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) + Undertake Digital IC Design processes & Perform design synthesis, linting + Complete projects from conception to completion Skills Required: + Experience with frontend … RTL Design + Strong Experience with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience – pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. A competitive salary, bonus More ❯

Social network you want to login/join with: Design Verification Engineer, south west london Client: ALOIS Solutions Location: south west london, United Kingdom Job Category: Other - EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 More ❯

Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯

Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯

ASIC and SoC design. We are looking for engineers with proven experience in several of the following areas: •Computer architectures (ARM or RISC-V) •SystemVerilog •UVM Verification •Digital verification using SystemVerilog, UVM, or cocotb •Formal Verification •Interconnect protocols such as AXI or OCP •ASIC tool flows •Familiarity with computer graphics More ❯

Social network you want to login/join with: At Dabster, we specialize in connecting top talent with leading global companies. We are currently seeking an experienced RTL Engineer to join our client's team. Our mission is to be More ❯