26 to 50 of 55 SystemVerilog Jobs in the UK

close coverage, and uncover deep functional bugs Required Skills & Experience Strong hands-on experience with formal verification tools Advanced proficiency in writing and debugging SystemVerilog Assertions Proven ability to tackle complex proof challenges and drive formal closure Experience with complementary formal flows such as: Design Property Verification (DPV). ...

designs meet performance, reliability, and maintainability requirements Hands-On FPGA Engineering Design, implement, and verify FPGA logic using VHDL and/or Verilog/SystemVerilog Work with high-speed interfaces, clocks, timing closure, and synchronization logic Integrate FPGA designs with embedded software, drivers, and system-level components Support bring … required Required Skills & Experience Strong experience in FPGA design and development in a production environment Proficiency in VHDL and/or Verilog/SystemVerilog Experience with FPGA toolchains (e.g. Xilinx/AMD, Intel/Altera) Solid understanding of: Clocking and timing constraints CDC, synchronization, and deterministic timing Debugging FPGA designs ...

edge sign-off methodologies. Key requirements: Mastery of industry-standard formal tools (e.g., JasperGold, VC Formal, or Questa Formal). Hands-on expertise writing SystemVerilog Assertions. PExperience in deep bug-hunting, coverage closure, and achieving formal sign-off on complex IPs. Knowledge of GPU architectures or sequential equivalence checking ...

youll do Define FPGA microarchitecture with a cross-functional team Implement RTL, including synthesis, timing closure, and debug Develop and execute unit-level verification (SystemVerilog) Build and validate FPGA prototypes for internal testing and customer trials What theyre looking for Strong industrial experience in high-speed FPGA design Hands … experience with high-end FPGA platforms Excellent RTL skills (SystemVerilog/Verilog/VHDL) Strong PCIe experience Broader software exposure (C/C++, Python) If you have the right skills and experience, wed love to hear from you! Apply today with your updated ...

Job Title: Staff GPU HW Design Engineer Location: United Kingdom Job Type: Permanent Full time Salary: DOE Role Overview: You’ll play a crucial role in designing, debugging, and optimising complex hardware modules to achieve ...

Role Overview: Youll play a crucial role in designing, debugging, and optimising complex hardware modules to achieve superior performance, efficiency, and reliability. You must be a British Citizen. There is no visa sponsorship available for ...

Staff ASIC Design Engineer This is a rare opportunity to apply your silicon design expertise to truly cutting-edge technology. Innovation sits at the core of this organisation, which develops foundational IP for market-leading ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

responsible for defining, implementing, and optimising RTL-level digital logic for complex ASIC and SoC designs. Key Responsibilities Translate architectural specifications into efficient, synthesizable SystemVerilog RTL. Develop detailed micro-architecture specifications for functional blocks and subsystems. Integrate IP blocks and ensure robust connectivity and data flow across the SoC. Requirements … Electrical Engineering, Computer Engineering, or a related discipline. 3+ years’ experience in digital logic/RTL design for ASIC or SoC projects. Strong SystemVerilog skills. Solid understanding of digital design fundamentals. Experience using EDA tools for simulation, synthesis, and linting. Familiarity with low-power design techniques, timing analysis, and common ...

Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans … Engineering or Computer Science 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans … Engineering or Computer Science 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

Design Verification Engineer This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on ...

Senior Design Verification Engineer - Bristol or Cambridge This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A ...

Lead the creation and verification of reusable RTL components A well-established company is seeking an RTL Design Architect with strong expertise in verification and good management skills to join their Cambridge-based development team. ...

create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design and DV engineers … Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland. Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE) I am looking for ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

everything from custom RTL designs to advanced compute and acceleration platforms . You’ll be involved in architecting and implementing complex systems in SystemVerilog , optimising data pipelines, and exploring new hardware technologies. The role is technical, hands-on, and focused on performance, efficiency, and robustness rather than domain knowledge … technologies, and architectures Contribute to a fast-moving, modern hardware development environment Key requirements: 2+ years’ experience in FPGA or ASIC RTL design Strong SystemVerilog expertise Deep understanding of FPGA/ASIC architectures and low-level hardware behaviour Experience with networking, data pipelines, or hardware acceleration (ML a plus) Working ...

Mixed Signal Verification Engineer A fantastic opportunity for an experienced Mixed Signal Verification Engineer to join an innovative leader in high-speed and energy-efficient chip-chip link solutions, critical to the evolution of the ...

open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage strategies Mentor engineers and drive best practices Collaborate with partners to support successful tapeouts Contribute … test and CI infrastructure Requirements: 8+ years in digital design verification with leadership experience Strong SystemVerilog/UVM skills Full verification lifecycle experience through tapeout C and/or Python for test automation Git/GitHub and team collaboration experience Nice to Have: Formal verification, RISC-V/ISA experience ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

Ensure the functional correctness and performance of complex digital ASIC Core/IP designs, including deep unit and core-level verification. Develop robust SystemVerilog/UVM verification environments. Create and execute tests to achieve high coverage and debug complex failures. Collaborate closely with design teams to deliver high-quality results. … Automate verification flows using Python or Perl scripts. What Were Looking For: 7+ years of hands-on experience in digital verification. Expertise in SystemVerilog/UVM and strong digital design knowledge. Experience verifying digital systems using standard IP components (e.g., microprocessor cores, hierarchical memory subsystems). Proficiency with EDA simulation ...

designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage Review open-source contributions and debug regressions Contribute to test and CI infrastructure Collaborate with partners … support successful tapeouts Requirements Essential 5+ years industry experience in design verification Strong SystemVerilog and UVM experience Full verification lifecycle experience through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience Security ...