26 to 45 of 45 SystemVerilog Jobs in the UK excluding London

Bristol Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

Stevenage Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

Stevenage Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPG... ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPG. . click apply for full job details ...

designs meet performance, reliability, and maintainability requirements Hands-On FPGA Engineering Design, implement, and verify FPGA logic using VHDL and/or Verilog/SystemVerilog Work with high-speed interfaces, clocks, timing closure, and synchronization logic Integrate FPGA designs with embedded software, drivers, and system-level components Support bring … required Required Skills & Experience Strong experience in FPGA design and development in a production environment Proficiency in VHDL and/or Verilog/SystemVerilog Experience with FPGA toolchains (e.g. Xilinx/AMD, Intel/Altera) Solid understanding of: Clocking and timing constraints CDC, synchronization, and deterministic timing Debugging FPGA designs ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place …/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/ ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place … AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/ ...

Staff ASIC Design Engineer This is a rare opportunity to apply your silicon design expertise to truly cutting-edge technology. Innovation sits at the core of this organisation, which develops foundational IP for market-leading ...

different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used by industry leading Companies. Experience of working on projects with teams located internationally. … Formal Verification (Jasper Gold or VC_Formal) Practical experience or desire to learn: Translating design requirements into RTL Deriving functional requirements for verification Systemverilog UVM test benches Scripting languages & REST API’s (e.g. Perl/Python/TCL) Team player with good verbal and written communication skills Formal Verification Desirable ...

Lead the creation and verification of reusable RTL components A well-established company is seeking an RTL Design Architect with strong expertise in verification and good management skills to join their Cambridge-based development team. ...

Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland. Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE) I am looking for ...

Design Verification Engineer - CPU DV/Microprocessor Verification/SystemVerilog/UVM We are partnered with a global semiconductor company with a major engineering presence in Cambridge. They are looking for a CPU Design Verification Engineer to work on high performance CPU and SoC products across a broad range ...

designs, owning test plans, driving coverage closure, and supporting integration using industry-standard verification environments. Key Responsibilities Design and implement UVM/SystemVerilog verification environments Deliver constrained-random verification and achieve coverage sign-off Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5) Integrate and use Verification … with design, architecture, and SoC teams Essential Skills & Experience Strong experience as a Verification Engineer/Design Verification Engineer Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience in ASIC ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...

A Digital Design Engineer with proficiency in RTL coding and a background in the design of high speed digital circuits using advanced CMOS technologies will join the talented team of an exciting name in the ...

Verso Recruitment is collaborating with a prestigious client based in Cambridge, renowned for their work on cutting-edge technology. They are currently seeking the expertise of a Contract Digital IC Design Engineer to contribute to ...

including data paths, block functionality, and interfaces Define and execute Formal Property Verification (FPV) strategies and test plans Develop assertion-based verification environments using SystemVerilog Assertions (SVA) Debug RTL issues and drive formal sign-off and coverage closure Collaborate closely with RTL design, architecture, and dynamic verification teams across global … Formal Verification within ASIC, SoC, or GPU-adjacent environments Strong hands-on experience with industry-standard formal verification tools Proven expertise writing and debugging SystemVerilog Assertions (SVA) Experience achieving formal coverage closure and sign-off Strong RTL debug and problem-solving skills Excellent communication skills and ability to work cross ...