Bristol, Avon, South West, United Kingdom Hybrid / WFH Options
Ernest Gordon Recruitment
Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the potential to increase your … turnover in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a … full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in More ❯
Bristol, Avon, South West, United Kingdom Hybrid / WFH Options
Ernest Gordon Recruitment
Engineer (Training and Progression) £30,000 - £35,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you an aspiring Verification Engineer looking to grow your expertise in SystemVerilog and UVM within a world-leading semiconductor company offering industry-leading training, structured progression, and the opportunity to increase your earnings through a 10% company bonus? This leading semiconductor and … global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you'll work closely with experienced verification engineers to develop and maintain SystemVerilog - UVM test benches, assist in creating and integrating new verification components and debugging test cases. You'll receive hands-on training, tailored development plans, and support to enhance your technical … a full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This position would suit an aspiring Verification Engineer with foundational SystemVerilog and UVM knowledge, looking to join a global semiconductor leader that prioritises growth, professional development, and long-term career progression and the opportunity to boost earnings through a company bonus. More ❯
Milton, Cambridgeshire, United Kingdom Hybrid / WFH Options
Verso Recruitment Group
Verso Recruitment is collaborating with a prestigious client based in Cambridge, renowned for their work on cutting-edge technology. They are currently seeking the expertise of a Contract Digital IC Design Engineer to contribute to an exciting new project. This More ❯
Cambridge, Milton, Cambridgeshire, United Kingdom Hybrid / WFH Options
Verso Recruitment Group
Verso Recruitment is collaborating with a prestigious client based in Cambridge, renowned for their work on cutting-edge technology. They are currently seeking the expertise of a Contract Digital IC Design Engineer to contribute to an exciting new project. This More ❯
Bristol, Gloucestershire, United Kingdom Hybrid / WFH Options
Ernest Gordon Recruitment Limited
Development Verification Engineer 55,000 - 65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the potential to increase your … turnover in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a … full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in More ❯