Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication More ❯
Hertfordshire, South East, United Kingdom Hybrid / WFH Options
Microtech Global Ltd
get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs Requirements: 5+ … years experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these roles are More ❯
working on a diverse range of projects that will both challenge and develop your technical and verification skills. You will have a good understanding of different methodologies, particularly SystemVerilog, UVM and MS-UCM. You will have the ability to quickly assimilate the verification challenge and help define an effective (and pragmatic) verification strategy and gain the support of the end More ❯
Hertfordshire, England, United Kingdom Hybrid / WFH Options
microTECH Global LTD
IP. The role offers a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL or Vulkan APIs is a plus More ❯
self-starting, and collaborative Ability to troubleshoot complex issues across teams and languages Experience with verification in CPU and/or ASIC environments Knowledge of SystemVerilog, Python, C++, Linux, UVM, SVA, Assembly, LLVM, GCC, Git, SGE or other DRS Familiarity with XML, XPath/XSLT We offer a competitive salary, flexible working, generous leave, private medical insurance, dental, pension (up More ❯
and recommending hardware or firmware-level fixes. Ability to lead technical discussions across architecture, firmware, software, and validation teams. "Nice To Have" Skills and Experience : Familiarity with RTL design, UVM/SystemVerilog, or hardware verification flows. Experience with trusted execution environments (TEEs) and secure monitor implementation. Understanding of secure firmware update mechanisms (rollback protection, anti-cloning). Prior work with More ❯
Job Description Job Title: UVMVerification Engineer Job Type: Contract Duration: 6 months initial Location: UK/Remote Start: ASAP For our UK based client we require a Verification Engineer to join on an initial 6 month basis. The successful engineer will join an established team on a project ramp-up. Required Skills - Strong Verification background, preferably at IP/… Module level - Expertise in hardware verification languages in particular SV UVMmethodology - Available to work on long-term contract (at least one year) - An interest in creating re-usable Verification IP, following guidelines for code and structure - A good listener who will gain a clear knowledge of what is required and is not afraid to ask any questions in order More ❯
work. You might also have: Knowledge of GPU/CPU architecture. Knowledge of standard bus protocols (e.g., AMBA5 CHI, AMBA4 ACE or AXI). Experience in wider verification technologies (UVM, etc.). Knowledge of a scripting language and/or C/SystemC. Understanding of functional safety standards such as ISO26262. If you are interested in this opportunity, please send More ❯
