101 to 111 of 111 SystemVerilog Jobs in the UK excluding London

Lead the creation and verification of reusable RTL components A well-established company is seeking an RTL Design Architect with strong expertise in verification and good management skills to join their Cambridge-based development team. ...

Report.Architectural Collaboration: Partner closely with Systems and Design Engineering teams to contribute to top-down chip architecture definitions and pre-design feasibility studies.UVM/SystemVerilog Testbench Architecture: Architect and construct robust, scalable, object-oriented SystemVerilog/UVM testbenches (including Scoreboards, Sequencers, Drivers, and Monitors) and class objects to be easily … verification plans, managing execution schedules, tracking regression metrics, and driving functional and code coverage closure for tape-out sign-off Technical Expertise:Expertise in SystemVerilog, SVA (Assertions), and UVM methodologies.Proficiency in scripting languages (e.g., Python, Bash, Perl) to drive automation and efficiency.Strong familiarity with Cadence mixed-signal simulation environments.Behavioral Modeling ...

work alongside experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate … quality silicon. Participate in code reviews and contribute to open-source projects. Requirements Essential 15 years' industry experience in Digital Design Verification. Experience with SystemVerilog and UVM. Understanding of verification methodologies and constrained-random verification. Experience writing testbenches and debugging RTL. Programming experience in Python and/or C. Familiarity ...

development. What you'll be doing Leading the verification of complex digital IP blocks from planning through to sign-off Developing and maintaining advanced SystemVerilog/UVM verification environments Creating functional coverage models and constrained-random test scenarios Driving coverage closure and ensuring verification quality targets are achieved Debugging complex … looking for Degree in Electronic Engineering, Electrical Engineering or a related discipline 8+ years' experience in Digital Verification Strong hands-on experience with SystemVerilog and UVM Proven experience verifying complex IP or SoC designs Strong understanding of constrained-random verification and coverage-driven methodologies Excellent debugging and problem-solving skills ...

Great opportunity for a Senior staff Verification Engineer to join a global R&D network. As a Staff Verification Engineer, you will take ownership of IP verification topics for cutting-edge designs of the future ...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in ...

development lifecycle. This is a hands-on verification role covering everything from planning and testbench development through to coverage closure and debugging. Responsibilities Develop SystemVerilog and UVM verification environments Create reusable verification components and testbenches Write assertions and functional coverage Debug complex RTL and simulation issues Drive verification activities from … sign-off Work closely with cross-functional engineering teams Help improve verification methodology and best practice About You You'll ideally have experience with: SystemVerilog UVM ASIC or SoC Verification Functional Coverage SystemVerilog Assertions (SVA) RTL Debug Verification Planning Experience within automotive or safety-critical semiconductor development would be beneficial ...

ASIC/SoC verification lifecycle, with real ownership of the verification of complex digital subsystems and mixed-signal ICs. Your work will include: Developing SystemVerilog/UVM verification environments Verification planning and test development Constrained-random and coverage-driven verification SVA/assertions Functional and code coverage RTL and testbench … senior levels What they're looking for You'll ideally have a background in ASIC, SoC or Digital IC Verification, with strong experience in: SystemVerilog | UVM | SVA | Constrained Random Verification | Functional Coverage | RTL Debug Experience with mixed-signal verification, formal verification, UPF/low-power verification, gate-level simulation ...

Job Description:We are looking for a skilled and motivated Functional Safety Engineer to join Arm's GPU Safety team.In this role, you will help deliver functional safety solutions for next-generation GPU products targeting ...

plus bonus and RSUs on top. The role Lead and mentor a small verification team Define and execute verification strategy (UVM/SystemVerilog) Oversee functional + formal verification Collaborate with design & architecture teams Drive coverage, quality, and delivery What you’ll bring Strong design verification background (digital or mixed-signal … Experience leading small teams or projects Skills in SystemVerilog, UVM, assertions, coverage Exposure to mixed-signal/ASIC environments (RNM a bonus) Why join Work on globally deployed technology Clear path into technical leadership Relocation support available High-impact role in a growing, innovative business Who this suits Senior Engineers ...

enjoys digging into complex hardware problems and working closely with architecture and design. The work involves: Leading verification of GPU components and subsystems Developing SystemVerilog/UVM testbenches Defining verification plans and coverage strategy Writing tests, sequences, assertions and functional coverage Debugging complex RTL issues with design engineers Contributing … methodology and mentoring others They’re hoping to find someone with: Strong experience verifying complex RTL/ASIC/SoC designs Deep SystemVerilog and UVM experience Background building constrained-random environments Solid debugging and root-cause skills Familiarity with ASIC verification flows and closure It’s a small, highly technical ...