126 to 150 of 224 SystemVerilog Jobs in the UK

Job Description Salary: £60,000 to £84,955 Leonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring ...

test complex IPs such as Crypto Accelerators and PCIe controllers, ensuring they function with software and other subsystems. You will write test plans, develop SystemVerilog testbenches, and collaborate with cross-functional teams to deliver robust IPs for diverse market sectors. #J-18808-Ljbffr ...

will build verification environments, write test plans, diagnose issues, and drive coverage closure across power, security and performance. A background in UVM/SystemVerilog or formal verification and a passion for open source are #J-18808-Ljbffr ...

will develop RTL, SDC/UPF constraints, integrate IPs and work with verification and implementation teams to ensure high‐quality designs. The role requires SystemVerilog/Verilog HDL skills, strong RTL design grounding, UNIX scripting, and collaboration across CPU, GPU, multimedia IP. #J-18808-Ljbffr ...

Technologies International Ltd in Cambridge seeks an ASIC verification specialist with hands-on FPV experience to advance GPU RTL verification pipelines. You will write SystemVerilog assertions, develop formal testbenches, and collaborate with global teams to achieve formal sign-off using JasperGold and related tools. Qualifications include a Bachelor’s degree ...

complex IPs such as Crypto Accelerators, HW DVFS components, PCIe controllers, and interconnect fabrics, ensuring integration with software. You will write test plans, develop SystemVerilog testbenches and C-based tests, debug failures and collaborate across multiple engineering teams to enable robust, high-quality silicon solutions. #J-18808-Ljbffr ...

ASIC Verification Engineer specializing in Formal Property Verification (FPV) to join the Engineering Group > ASICS Engineering. You will develop FPV test plans, write SystemVerilog Assertions, and collaborate with global RTL design and DV teams to drive sign-off. The role requires 2+ years in ASIC design/verification, a degree ...

London. The role involves delivering emulation capabilities for GPU designs while collaborating with design and software teams. Candidates should have strong knowledge in SystemVerilog, debugging skills, and proficiency in programming languages such as Python, C, and C++. The position offers the opportunity to innovate and be part of a dynamic ...

complex, large-scale GPU projects. This role involves micro-architecture development, logic synthesis, and debugging of design issues. Ideal candidates will have experience with SystemVerilog, VHDL, and strong problem-solving skills. The team values diverse perspectives, promoting an inclusive work environment. Join us to influence the design flow of cutting ...

verification for complex CPUs and CHERI-enabled technologies within UK design centres in Cambridge or Bristol. Ideal candidates have hands-on experience with SystemVerilog, Python, C++, and Rust, plus Linux automation, and a solid understanding of CPU architectures. #J-18808-Ljbffr ...

algorithm modelling to RTL sign-off and silicon bring-up. You will collaborate with digital design, optics, and software teams, develop verification environments with SystemVerilog/UVM, constrained-random testing, and formal methods, and contribute to reusable verification methodologies while mentoring junior engineers. #J-18808-Ljbffr ...

will develop UVM testbenches, lead verification activities, and ensure project closure through metrics tracking. The ideal candidate will demonstrate strong expertise in verification methodologies, SystemVerilog, and communication skills to collaborate effectively across teams. By joining us, you will contribute to cutting-edge graphics technology utilized worldwide. Embrace the opportunity ...

with engineering teams to ensure customer feedback is channelled into product improvements Key requirements: Strong background in digital hardware design (Verilog/VHDL/SystemVerilog) Experience with AMBA protocols (AXI, AHB, APB) Deep understanding of IP integration and SoC architecture Familiarity with Network-on-Chip (NOC) design and implementation Excellent ...

gate-level simulation, etc.)Knowledge of verifying CPU architectures or other IPFluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, etc. Past verification ownership of a design blockUser knowledge of Linux to enable automation of common tasksKnowledge of versioning tools ...

level simulation, etc.) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, etc. Past verification ownership of a design block User knowledge of Linux to enable automation of common tasks Knowledge of versioning tools ...

incident response workflows for Fractile's infrastructure. IaC TODO Scale and maintain Fractile's Bazel monorepo as we continue growing across Python, C++, Rust, SystemVerilog, and ML workloads. Shape the infrastructure and platform experience for every engineer at Fractile. About You You bring deep infrastructure and build systems expertise alongside ...

Contribute to the design, implementation, verification, and delivery of high-performance digital hardware IP for wireless communication systems Develop RTL designs using SystemVerilog, Verilog, or VHDL for FPGA and ASIC technologies Support development and verification of communications signal processing functions and hardware architectures Collaborate with hardware, algorithm, software, and systems … related technical discipline Understanding of digital design fundamentals, including combinational and sequential logic, finite state machines, timing concepts, and digital architectures Exposure to Verilog, SystemVerilog, or VHDL through academic projects, placements, internships, or personal projects Basic knowledge of Python, MATLAB, Tcl, or Bash Strong analytical, problem-solving, and debugging skills ...

compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low‐level C software for FPGA bring‐up, test, and integration. Use industry‐standard tools such as Vivado, Quartus … consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real‐time, high‐speed, or RF‐centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA‐host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm‐to‐hardware workflows. Proven ability ...

compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low-level C software for FPGA bring-up, test, and integration. Use industry-standard tools such as Vivado, Quartus … consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real-time, high-speed, or RF-centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm-to-hardware workflows. Proven ability ...

## Firmware/FPGA Engineers - all levelsApplylocations: GB - Edinburgh: GB - Newcastletime type: Full timeposted on: Posted Todayjob requisition id: R0030762**Job Description:**Salary: Engineer: £37,400 to £53,550/Senior: £45, 200 to £61 ...

Job Description: Salary: Engineer: 37,400 to 53,550/Senior: 45, 200 to 61,950/Principal: 53,300 to 71,400/Lead: 59,400 to 84,955Leonardo UK operates a grade-based ...

constrained-random testing, and drive verification closure across RTL designs. You will collaborate with design and verification teams on tape-out-ready blocks, apply SystemVerilog/UVM, and leverage formal verification to expose corner cases, contributing to scalable, high-performance processors. #J-18808-Ljbffr ...

fast-paced environment. You will define verification strategies, run simulations, hunt bugs, and drive root-cause analyses while crafting automated verification flows using SystemVerilog, Python, C++, or Rust on Linux with Git/SVN for automation. #J-18808-Ljbffr ...

open-source silicon team. This permanent, hybrid role offers involvement in OpenTitan Root of Trust and Ibex CPU verification. You will develop and debug SystemVerilog/UVM testbenches, create verification plans, and collaborate with design engineers to deliver high-quality silicon, while contributing to open-source projects and robust verification ...

create advanced silicon solutions, preparing detailed design specifications, and optimising hardware modules. The ideal candidate should have hands-on experience in RTL design using SystemVerilog, strong analytical skills, and a commitment to quality outcomes. Join a company that powers next-gen mobile and smart technologies and enables significant market impact. ...