151 to 175 of 323 SystemVerilog Jobs in the UK excluding London

the implementation approach and details of a testbench Be able to do root-cause analysis of complex issues and resolve them in a timely manner Have excellent knowledge of SystemVerilog and UVM Be able to develop new verification flows Have working knowledge of ASIC design methodologies, flows and tools Be able to plan, estimate and track your own work Experience More ❯

a passion for innovation. Depending on your experience, you'll bring some, or all, of the following: Experience in design techniques using VHDL Experience in verification techniques using eitherVHDLor SystemVerilog/UVM. Experience in specifying timing and area constraints forefficientFPGA place and route. Ability toanalysesystem level requirements and derive detailedfirmwarerequirements. Degree (BSc, BEng, MEng, MSc, PhD, EngD) in Electrical &Electronic More ❯

Synplify Pro Standards, Frameworks and Techniques Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC26262, DO 254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python We're an equal opportunities employer. We're committed to developing a diverse workforce and an inclusive working environment. We believe that people from different backgrounds and cultures More ❯

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building More ❯

Job Description As a Digital Design Engineer, you will be responsible for the digital design and RTL coding using Verilog or System Verilog. Integrating modules at SoC and work hands-on in the development cycle, especially in frontend domain until More ❯

AI compute fabrics. Your work will ensure first‐silicon success and robust, production‐worthy silicon that scales to data‐centre volumes. Responsibilities Architect, implement and maintain comprehensive verification environments (SystemVerilog + UVM, assertion‐based and formal) for datapath, control, memory and high‐speed I/O blocks in our OTPU. Define verification plans that target functional correctness, low‐power modes … techniques to keep Flux at the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low‐power (UPF/CPF) methodologies. More ❯

Python. Knowledge of thermal and mechanical considerations in hardware design. Experience using PCIe, CXL, RDMA, DDR4, bare metal use of high-speed transceivers, Ethernet, IP. Good experience in FPGA, SystemVerilog/Verilog/VHDL. The company offer an excellent salary, along with a bonus up to 85%, flexible and hybrid working, exciting technology and a great team working environment in More ❯

design and architecture, with a strong understanding of VHDL and SystemVerilog. Proficiency in FPGA design toolsets and verification tools (QuestaSim, ModelSim). Verifying complex FPGA designs with VHDL and SystemVerilog/UVM test-bench methodologies. Generating low-level software (C) for FPGA test and integration with embedded systems. Eligibility for security clearance (British citizenship or dual UK nationality may be More ❯

performance. What We’re Looking For in a Design for Test (DFT) Engineer: Proven Expertise in DFT engineering, with a strong record of technical innovation. Technical Proficiency : Skilled in SystemVerilog RTL, TCL, Python, and Unix/Linux environments. Core DFT Competencies : Experience with hierarchical scan, memory BIST, JTAG/IJTAG, at-speed testing, ATPG, fault simulation, and silicon debug. Tools More ❯

Fi, SDIO/eMMC, MIPI CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features Expert-level Verilog/SystemVerilog for design and verification Familiarity with scripting languages (Bash, Python, Tcl, etc) The following would also be useful: Experience of Cadence simulation tool flow Experience with ASIC/FPGA synthesis More ❯

DOORS, Siemens QuestaSim/ModelSim, Synopsys Synplify Pro, and knowledge of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254, as well as languages like VHDL, SystemVerilog, TCL, Python. The package includes a competitive salary (dependent on experience), pension, life assurance, 25 days' holiday plus bank holidays, and opportunities for training and career development. Note: UK defence More ❯

Need From You We value technical expertise and passion for innovation. Depending on your experience, you should have: Experience in VHDL design techniques. Experience in verification using VHDL or SystemVerilog/UVM. Knowledge of timing and area constraints for FPGA design. Ability to analyze system requirements and derive detailed firmware specifications. Degree in Electrical & Electronic Engineering or similar. Security Clearance More ❯

regular mentoring, coaching, and feedback Skills, Knowledge & Expertise Essential Skills and Experience: Track record of building and leading high performing collaborative teams Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivery of digital designs for ASIC and FPGA Optimisation of timing and hardware resources for high throughput data or signal More ❯

imaging systems. The position is based in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Define concepts for digital SoC architecture and blocks Create specifications Design and verify RTL (SystemVerilog/VHDL/FPGA) Collaborate closely with analog IC designers and subcontractors Experience with synthesis, timing closure, and STA is highly desirable Support DfT strategy and implementation Debug RTL and More ❯

Pro Standards, Frameworks and Techniques: Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python The package: You'll receive a very competitive salary ( offered depends on level of experience) and other benefits including pension, life assurance and 25 days' (plus bank holidays More ❯

and planning skills Motivated, self-starting, and collaborative Ability to troubleshoot complex issues across teams and languages Experience with verification in CPU and/or ASIC environments Knowledge of SystemVerilog, Python, C++, Linux, UVM, SVA, Assembly, LLVM, GCC, Git, SGE or other DRS Familiarity with XML, XPath/XSLT We offer a competitive salary, flexible working, generous leave, private medical More ❯

SOC-level verification Ability to determine verification requirements from the analysis of specifications Experience of debug and testing methodologies Experience with industry-standard verification methodologies and tools (UVM/SystemVerilog, Tools like VCS/Cadence/Questa) Experience in version control systems (e.g., Git/Mercurial/Perforce/Subversion) You might also have: A background in digital design Confident More ❯

Engineering or related. Additional Job Description: Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys. Be fluent in SystemVerilog, Verilog or VHDL and familiar with LINT, simulation and synthesis. Familiarity with architectures for secure systems design, e.g., cryptographic encoders/decoders or tagged processor architectures is a plus. Demonstrated More ❯

for defining, estimating and tracking of own work YOU SHOULD HAVE: Over 2 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools (Git, SVN) Knowledge of More ❯

for defining, estimating and tracking of own work YOU SHOULD HAVE: Over 2 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools (Git, SVN) Knowledge of More ❯

Join to apply for the Senior Firmware Engineer role at Fortescue 3 days ago Be among the first 25 applicants Join to apply for the Senior Firmware Engineer role at Fortescue Get AI-powered advice on this job and more More ❯

in every design you deliver. What You’ll Do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

record in delivering 1st time success with complex mixed signal IC's. Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis SystemVerilog - SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Strong ability to interpret results and resolve More ❯

verification processes and methodologies Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Solid understanding and hands-on experience with UVM and SystemVerilog Proficiency in scripting languages such as Perl, Python, or TCL Mid-Senior level As a Design Verification Engineer, the individual will spend their days collaborating with design and verification teams More ❯

have: •A degree in Electrical Engineering, Computer Engineering, or a related field •A basic understanding of digital design principles and computer architecture •Exposure to RTL design languages such as SystemVerilog or VHDL (through coursework, projects, or internships) •An interest in GPUs, AI accelerators, or RISC-V architecture •Some experience or enthusiasm for scripting (e.g., Python, TCL More ❯