101 to 107 of 107 UVM Jobs in the UK excluding London

verification engineers, while remaining hands-on in technical execution. Responsibilities Define and execute verification strategies for WiFi SoC ASIC designs Develop and implement UVM-based testbenches and environments in SystemVerilog Collaborate with cross-functional design and architecture teams to ensure first-time success Mentor and guide junior verification engineers … Electrical/Computer Engineering or related discipline Proven track record in ASIC verification, ideally with experience in complex SoC designs Proficiency in SystemVerilog and UVM methodology WiFi or wireless SoC experience is highly desirable Strong leadership skills with the ability to mentor and influence Excellent communication and collaboration skills What ...

verification engineers, while remaining hands-on in technical execution. Responsibilities Define and execute verification strategies for WiFi SoC ASIC designs Develop and implement UVM-based testbenches and environments in SystemVerilog Collaborate with cross-functional design and architecture teams to ensure first-time success Mentor and guide junior verification engineers … Electrical/Computer Engineering or related discipline Proven track record in ASIC verification , ideally with experience in complex SoC designs Proficiency in SystemVerilog and UVM methodology WiFi or wireless SoC experience is highly desirable Strong leadership skills with the ability to mentor and influence Excellent communication and collaboration skills What ...

with design and system teams. The focus is on building and maintaining robust verification environments and validating complex algorithms. Key Responsibilities Develop and maintain UVM, class-based verification testbenches Verify DSP/RF signal-chain blocks including FFT, FIR filters and channelizers Integrate VIP and drive constrained-random and coverage … using Git Support ASIC/SoC/FPGA verification flows Essential Skills & Experience Strong experience as a Verification Engineer/ASIC Verification Engineer Proven UVM and class-based verification expertise Solid background in DSP verification (FFT, FIR, signal processing) Python for automation and regression Experience with SoC/ASIC/ ...

complex IP and SoC designs, owning test plans, driving coverage closure, and supporting integration using industry-standard verification environments. Key Responsibilities Design and implement UVM/SystemVerilog verification environments Deliver constrained-random verification and achieve coverage sign-off Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5 … workflows Collaborate with design, architecture, and SoC teams Essential Skills & Experience Strong experience as a Verification Engineer/Design Verification Engineer Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience ...

Digital Verification Engineer with a strong Semiconductor background involving the verification of complex designs (FPGA or ASIC) and with some UVM experience are sought by an exciting new name in the Semiconductor industry. Competitive salary plus Hybrid working, Shares and good benefits. The successful Digital Verification Engineer will work with … Electrical Engineering related discipline. 5+ years experience working within the semiconductor industry ( 10+ for Lead level). Extensive experience of digital verification with some UVM experience. Track record of verifying complex designs (FPGA/ASIC) ideally in high volume applications. Strong Scripting skills. Deep knowledge of simulation tools and debugging ...

Responsibilities: Develop and execute UVM testbenches for unit-level and sub-system verification Perform coverage analysis and drive coverage closure to ensure verification completeness Work with PCIe, AMBA CHI, and AXI protocols for system verification Collaborate with design and verification teams to ensure timely delivery of high-quality designs Required … Skills & Experience: Strong experience with PCIe protocol verification Expertise in UVM methodology for both unit-level and sub-system level verification Hands-on experience with AMBA CHI & AXI interfaces Proven experience in coverage analysis and closure Strong problem-solving and debugging skills in a collaborative team environment Working Pattern ...

signal ASIC designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog testbenches. Write, debug, and execute test cases to verify functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation … improvement of design and verification best practices Qualifications 5+ years’ experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting languages ...