51 to 69 of 69 SystemVerilog Jobs

Design Verification Engineer This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on ...

Senior Design Verification Engineer - Bristol or Cambridge This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A ...

create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design and DV engineers … Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland. Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE) I am looking for ...

Lead the creation and verification of reusable RTL components A well-established company is seeking an RTL Design Architect with strong expertise in verification and good management skills to join their Cambridge-based development team. ...

Design Verification Engineer - CPU DV/Microprocessor Verification/SystemVerilog/UVM We are partnered with a global semiconductor company with a major engineering presence in Cambridge. They are looking for a CPU Design Verification Engineer to work on high performance CPU and SoC products across a broad range ...

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...

everything from custom RTL designs to advanced compute and acceleration platforms . You’ll be involved in architecting and implementing complex systems in SystemVerilog , optimising data pipelines, and exploring new hardware technologies. The role is technical, hands-on, and focused on performance, efficiency, and robustness rather than domain knowledge … technologies, and architectures Contribute to a fast-moving, modern hardware development environment Key requirements: 2+ years’ experience in FPGA or ASIC RTL design Strong SystemVerilog expertise Deep understanding of FPGA/ASIC architectures and low-level hardware behaviour Experience with networking, data pipelines, or hardware acceleration (ML a plus) Working ...

Mixed Signal Verification Engineer A fantastic opportunity for an experienced Mixed Signal Verification Engineer to join an innovative leader in high-speed and energy-efficient chip-chip link solutions, critical to the evolution of the ...

open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage strategies Mentor engineers and drive best practices Collaborate with partners to support successful tapeouts Contribute … test and CI infrastructure Requirements: 8+ years in digital design verification with leadership experience Strong SystemVerilog/UVM skills Full verification lifecycle experience through tapeout C and/or Python for test automation Git/GitHub and team collaboration experience Nice to Have: Formal verification, RISC-V/ISA experience ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

Ensure the functional correctness and performance of complex digital ASIC Core/IP designs, including deep unit and core-level verification. Develop robust SystemVerilog/UVM verification environments. Create and execute tests to achieve high coverage and debug complex failures. Collaborate closely with design teams to deliver high-quality results. … Automate verification flows using Python or Perl scripts. What Were Looking For: 7+ years of hands-on experience in digital verification. Expertise in SystemVerilog/UVM and strong digital design knowledge. Experience verifying digital systems using standard IP components (e.g., microprocessor cores, hierarchical memory subsystems). Proficiency with EDA simulation ...

designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage Review open-source contributions and debug regressions Contribute to test and CI infrastructure Collaborate with partners … support successful tapeouts Requirements Essential 5+ years industry experience in design verification Strong SystemVerilog and UVM experience Full verification lifecycle experience through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience Security ...

designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage Review open-source contributions and debug regressions Contribute to test and CI infrastructure Collaborate with partners … support successful tapeouts Requirements Essential 5 years industry experience xkybehq in design verification Strong SystemVerilog and UVM experience Full verification lifecycle experience through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience ...

designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog testbenches. Write, debug, and execute test cases to verify functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation, coverage analysis … continuous improvement of design and verification best practices Qualifications 5+ years’ experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting ...

A Digital Design Engineer with strong RTL coding skills and a background in the design of high-speed digital circuits will join the talented team of an exciting name in the Semiconductor industry. Rewarding opportunity ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...

Contract Terms Length: 6 Months Initial Rate: Of project budget Working Arrangement: Hybrid (Mostly Remote, occasional site visits) Start Date: ASAP Essential Skills Strong SystemVerilog Proven experience with UVM UVM testbench development from scratch Testbench architecture, stimulus generation, monitors, scoreboards Functional coverage definition and closure Verification of complex digital … Profile Skills Candidates with a mixed design/verification background are also of interest, provided verification skills are present: RTL exposure in Verilog/SystemVerilog Ability to read, understand, and occasionally modify RTL Experience collaborating on design-for-verification activities Additional Nice-to-Haves RS FEC exposure Experience in verification ...

A leading semiconductor company in Limerick is seeking a Principal Design Verification Engineer to develop cutting-edge silicon solutions for Industry 4.0. This senior role involves architecting UVM-based testbench environments, defining verification strategies, and ...