101 to 125 of 326 SystemVerilog Jobs in the UK

of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of multiple design blocks Analytical thinking, self-sufficiency and strong team collaboration skills Ability to work effectively More ❯

MSc or PhD degree qualification in Electronics/Computer Engineering or equivalent Ability to understand and use Hardware Description Languages (HDLs) such as Verilog, SystemVerilog or VHDL Strong interest in and understanding of CPU architectures and SoC design principles Experience in using RTL simulation tools for debugging purposes Ability to More ❯

designs are developed according to relevant standards • Manage engineers • Conduct peer reviews Competences and Skills Essential • Full lifecycle of electronics design • VHDL, Verilog, or SystemVerilog • Simulators, synthesis and place & route tools and hardware debug • Verification methodologies • Scripting languages (e.g. Python) • Revision Control Systems (e.g. Git or Subversion) Flexible working You More ❯

feedback and who can independently define the scope of work. Proven experience of testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. You have formal verification experience. What you can expect from us More ❯

of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning More ❯

with 1-5 years of experience. Responsibilities Development of Wi-Fi products, including microcontrollers and connectivity. Test bench and test case generation using Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial experience. More ❯

to offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources More ❯

Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. More ❯

Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. More ❯

Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. More ❯

its core tech group if you’re not keen working on trading desks. Requirements At least 5+ years’ hands-on development experience in HDL (SystemVerilog/VHDL) with C++ knowledge Solid experience in solving numerical problems with existing commercial architectures (CPU/GPU/FPGA/etc.) Sound knowledge of More ❯

ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone More ❯

to offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources More ❯

leadership What You ll Bring 5+ years in firmware/FPGA design, with experience in architecture or technical leadership Deep knowledge of VHDL/SystemVerilog, high-speed digital design, and simulation Comfortable capturing and refining requirements from stakeholders Experience in defence, aerospace, or safety-critical embedded systems preferred Eligibility for More ❯

leadership What You'll Bring 5+ years in firmware/FPGA design, with experience in architecture or technical leadership Deep knowledge of VHDL/SystemVerilog, high-speed digital design, and simulation Comfortable capturing and refining requirements from stakeholders Experience in defence, aerospace, or safety-critical embedded systems preferred Eligibility for More ❯

ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone More ❯

ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone More ❯

level simulation etc ) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Analytical thinking and team collaboration skills What we'd love you to have Past verification ownership of a design block More ❯

field. Master's degree preferred. Experience: Extensive experience in design verification, including team and/or project leadership roles. Skills: Proficiency in verification languages (SystemVerilog, UVM), strong analytical and problem-solving skills, excellent communication and leadership abilities. Knowledge of mixed-signal ASIC architectures, real number modelling, constrained random, assertions, gate More ❯

verification reports demonstrating all tests passing on RTL. Utilize verification methodologies including design checks, simulation, emulation, UVM, formal verification, and testbenches in Verilog/SystemVerilog and C. #J-18808-Ljbffr More ❯

a key Defence client. Requirements Experience with Xilinx products Understanding of DSP VHDL encoding in a Linux environment Knowledge of Verilog and/or SystemVerilog Active SC clearance required Application Process Please apply online or email me directly (see below). For further information, call me. If unavailable, leave a More ❯

low area, and understanding of how RTL will map to gate-level structures Familiarity with the frontend design flow Experience with hardware description languages - SystemVerilog would be desirable You must be able to relocate to Bristol or already be based in the City. Base and Bonus are on offer. Hybrid More ❯

CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features. Expert-level Verilog/SystemVerilog for design and verification. Familiarity with scripting languages. The following would also be useful: The role is based on site in Cambridge with an expectation More ❯

CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features. Expert-level Verilog/SystemVerilog for design and verification. Familiarity with scripting languages. The following would also be useful: The role is based on site in Cambridge with an expectation More ❯

partners. Key Responsibilities: Define digital architectures for AI accelerators, data paths, control logic, and SoC subsystems. Develop high-quality, synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind. Collaborate cross-functionally with verification, physical design, and packaging teams to ensure seamless integration. Leverage Cadence digital More ❯